<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/arm/include/debug, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/arm/include/debug?h=jd%2Forphan-parallel</id>
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<updated>2020-09-15T13:35:28Z</updated>
<entry>
<title>ARM: 9005/1: debug: Select flow control for all debug UARTs</title>
<updated>2020-09-15T13:35:28Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-08-27T22:28:56Z</published>
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<id>urn:sha1:4df24fef09615d8f7dd2120f5072486addfd3eb9</id>
<content type='text'>
Instead of a flow control selection mechanism specifically for
8250, make this available for all debug UARTs. If the debug
UART supports waiting for CTS to be asserted, then this code
can be activated for terminals that need it.

We keep the defaults for EBSA110, Footbridge, Gemini and RPC
so that this still works as expected for these older platforms:
they assume that flow control shall be enabled for debug
prints.

I switch the location of the check for
ifdef CONFIG_DEBUG_UART_FLOW_CONTROL from the actual debug
UART drivers: the code would get compiled-out for 8250 and
Tegra unless their custom config (or passing -DFLOW_CONTROL
in the Tegra case) was not set. Instead this is conditional
at the three places where we print debug messages. The idea
is that debug UARTs can be implemented without this ifdef
boilerplate so they look cleaner, alas the ifdef has to be
somewhere.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@armlinux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: 9004/1: debug: Split waituart to CTS and TXRDY</title>
<updated>2020-09-15T13:35:27Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-08-27T22:25:37Z</published>
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<id>urn:sha1:2c50a570e9dc649c182268e779dffe0712e98a6a</id>
<content type='text'>
This patch was triggered by a remark from Russell that
introducing a call to the waituart (needed to fix debug prints
on the Qualcomm platforms) was dangerous because in some cases
this will involve waiting for a modem CTS (clear to send)
signal, and debug messages would maybe not work on platforms
with no modem connected to the UART port: they will just
hang waiting for the modem to assert CTS and this might never
happen.

Looking through all UART debug drivers implementing the waituart
macro I discovered that all users except two actually use this
macro to check if the UART is ready for TX, let's call this
TXRDY.

Only two debug UART drivers actually check for CTS:
- arch/arm/include/debug/8250.S
- arch/arm/include/debug/tegra.S

The former is very significant since the 8250 is possibly
the most common UART on the planet.

We have the following problem: the semantics of waituart are
ambiguous making it dangerous to introduce the macro to debug
code fixing debug prints for Qualcomm. To start to pry this
problem apart, this patch does the following:

- Convert all debug UART drivers to define two macros:

  - waituartcts with the clear semantic to wait for CTS
    to be asserted

  - waituarttxrdy with the clear semantic to wait for the TX
    capability of the UART to be ready

- When doing this take care to assign the right function to
  each drivers macro, so they now do exactly the above.

- Update the three sites in the kernel invoking the waituart
  macro to call waituartcts/waituarttxrdy in sequence, so that
  the functional impact on the kernel should be zero.

After this we can start to change the code sites using this
code to do the right thing.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@armlinux.org.uk&gt;
</content>
</entry>
<entry>
<title>ARM: debug: stm32: add UART early console support for STM32MP1</title>
<updated>2020-03-13T16:05:07Z</updated>
<author>
<name>Erwan Le Ray</name>
<email>erwan.leray@st.com</email>
</author>
<published>2020-02-03T14:04:25Z</published>
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<id>urn:sha1:62c1594d38805938e566b059573c0b1e49da6b70</id>
<content type='text'>
Add support of early console for STM32MP1. Default UART instance is UART4,
but other UART instances can be configured by setting physical and virtual
base addresses in menuconfig.

Signed-off-by: Erwan Le Ray &lt;erwan.leray@st.com&gt;
Signed-off-by: Alexandre Torgue &lt;alexandre.torgue@st.com&gt;
</content>
</entry>
<entry>
<title>ARM: debug: stm32: add UART early console support for STM32H7</title>
<updated>2020-03-13T16:05:07Z</updated>
<author>
<name>Erwan Le Ray</name>
<email>erwan.leray@st.com</email>
</author>
<published>2020-02-03T14:04:24Z</published>
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<id>urn:sha1:33cab8954abe719d0e19d5bba017cb1695d91d68</id>
<content type='text'>
Add support of early console for STM32H7. Default UART instance is USART1,
but other UART instances can be configured by setting physical and virtual
base addresses in menuconfig.

Signed-off-by: Erwan Le Ray &lt;erwan.leray@st.com&gt;
Signed-off-by: Alexandre Torgue &lt;alexandre.torgue@st.com&gt;
</content>
</entry>
<entry>
<title>ARM: debug: stm32: add UART early console configuration for STM32F4</title>
<updated>2020-03-13T16:05:07Z</updated>
<author>
<name>Erwan Le Ray</name>
<email>erwan.leray@st.com</email>
</author>
<published>2020-02-03T14:04:22Z</published>
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<id>urn:sha1:79d5cfd19d261b0e64569649b04867c8dbdcd8a9</id>
<content type='text'>
Early console is hardcoded on USART1 in current implementation.
With this patch, default UART instance is USART1, but other UART instances
can be configured by setting physical and virtual base addresses in
menuconfig.

Signed-off-by: Erwan Le Ray &lt;erwan.leray@st.com&gt;
Signed-off-by: Alexandre Torgue &lt;alexandre.torgue@st.com&gt;
</content>
</entry>
<entry>
<title>ARM: brcmstb: Add debug UART entry for 7216</title>
<updated>2019-12-20T18:54:05Z</updated>
<author>
<name>Justin Chen</name>
<email>justinpopo6@gmail.com</email>
</author>
<published>2019-12-10T22:48:56Z</published>
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<id>urn:sha1:064f42b28a6d6cfddc983cb433d52c3d3b006442</id>
<content type='text'>
7216 has the same memory map as 7278 and the same physical address for
the UART, alias the definition accordingly.

Signed-off-by: Justin Chen &lt;justinpopo6@gmail.com&gt;
[florian: expand commit message]
Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'renesas-arm-soc-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/soc</title>
<updated>2019-09-03T21:12:58Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-09-03T21:12:57Z</published>
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<id>urn:sha1:9e38081e5deb9c6cb7a7949b4f12959ea3ca8663</id>
<content type='text'>
Renesas ARM SoC updates for v5.4

  - Low-level debugging support for RZ/A2M.

* tag 'renesas-arm-soc-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: debug-ll: Add support for r7s9210

Link: https://lore.kernel.org/r/20190823123643.18799-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>ARM: debug-ll: Add support for r7s9210</title>
<updated>2019-08-21T09:15:26Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2019-06-03T07:37:19Z</published>
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<id>urn:sha1:e9670ccb39dbcfc934ae9533163e81a769d2cb82</id>
<content type='text'>
Enable low-level debugging support for RZ/A2M (r7s9210).

The RZA2MEVB board uses either SCIF2 (SDRAM enabled) or SCIF4 (HyperRAM
only) for the serial console.

Note that "SCIFA" serial ports on RZ/A2 SoCs use a compressed register
layout, hence add support for that to renesas-scif.S.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Reviewed-by: Simon Horman &lt;horms+renesas@verge.net.au&gt;
</content>
</entry>
<entry>
<title>Merge tag 'ux500-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into arm/soc</title>
<updated>2019-08-14T13:37:17Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-08-14T13:04:45Z</published>
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<id>urn:sha1:a3950da161a6fdb8099a00b936dcf848639f7ab6</id>
<content type='text'>
This is a slew of Ux500 updates for the v5.4 kernel cycle:

- Stop populating the PRCMU devices from the core CPU
  file, it works just fine at device_initcall() level.

- Add a missing of_node_put() in the core file.

- Simplify the debug UART code.

- Add myself to MAINTAINERS

* tag 'ux500-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
  MAINTAINERS: add soc/ux500
  ARM: ux500: simplify and move debug UART
  ARM: ux500: add missing of_node_put()
  ARM: ux500: Stop populating the PRCMU devices early

Link: https://lore.kernel.org/r/CACRpkdbH-h5fRwuidcpeOp8mtRoKUW65SAk8a4A==BCDzn3QMA@mail.gmail.com
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>ARM: remove ks8695 platform</title>
<updated>2019-08-14T13:03:52Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-08-09T20:27:29Z</published>
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<id>urn:sha1:c68b26697d2744d32df621e0ba9a17094bb37d6b</id>
<content type='text'>
ks8695 is an older SoC originally made by Kendin, which was later acquired
by Micrel, and subsequently by Microchip.

The platform port was originally contributed by Andrew Victor and Ben
Dooks, and later maintained by Greg Ungerer.

When I recently submitted cleanups, but Greg noted that the platform no
longer boots and nobody is using it any more, we decided to remove it.

Link: https://lore.kernel.org/r/20190809202749.742267-2-arnd@arndb.de
Cc: Andrew Victor &lt;linux@maxim.org.za&gt;
Acked-by: Ben Dooks &lt;ben-linux@fluff.org&gt;
Link: https://wikidevi.com/wiki/Micrel
Link: https://lore.kernel.org/linux-arm-kernel/2bc41895-d4f9-896c-0726-0b2862fcbf25@kernel.org/
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Greg Ungerer &lt;gerg@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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