wireguard-linux/arch/arm64/boot/dts/intel, branch stable

Merge tag 'dt64-cleanup-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

2026-08-10T16:01:37Z

Minor improvements in arm64 DTS for v7.3 Several non-functional (white-space and style) changes to match with DTS coding style as reported by recent dt-check-style tool. Goal is to get to no `dt-check-style --mode strict` warnings over time. * tag 'dt64-cleanup-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: arm64: dts: Correct white-space style arm64: dts: amd: seattle: Remove useless xgbe DTSI include arm64: dts: amd: seattle: Remove useless clocks DTSI include Signed-off-by: Arnd Bergmann

arm64: dts: Correct white-space style

2026-08-04T06:10:49Z

Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Michal Simek # Versal NET Acked-by: Sven Peter # for apple dts Link: https://patch.msgid.link/20260801210210.383417-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski

arm64: dts: socfpga: use consistent QSPI boot partition label

2026-07-28T03:09:15Z

Several SoCFPGA board DTS files labeled the first QSPI MTD partition (qspi_boot / partition@0 under fixed-partitions) as "u-boot" while others already used "Boot and fpga data". Align the QSPI boot partition label only so naming matches the combined boot + FPGA image layout and stays consistent across Agilex, N5X, and Stratix 10 SoCDK variants. No QSPI partition layout or reg properties are changed. Signed-off-by: Tze Yee Ng Signed-off-by: Dinh Nguyen

arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2

2026-06-29T16:42:20Z

Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs. Signed-off-by: Dinh Nguyen --- v2: no changes

arm64: dts: socfpga: agilex72: Add initial device tree

2026-06-29T11:52:28Z

Add initial device tree support for the Intel SoCFPGA Agilex72 platform. This introduces the SoC DTSI and the SoCDK board DTS as the first upstream submission for this platform. The Agilex72 SoC features a heterogeneous CPU cluster with Cortex-A520 and Cortex-A720 cores, and includes an SMMU v3 for memory management. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen

arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes

2026-06-29T11:52:28Z

The SMMU is enabled and transactions going through it are cache coherent. Add the dma-coherent property to the XGMAC nodes to prevent redundant cache flush/invalidate operations and potential stale data issues. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen

arm64: dts: socfpga: agilex5: Enable the SMMU

2026-06-29T11:52:28Z

The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different memory-mapped base address for its peripherals, which requires the SMMU to be active so that the Secure Device Manager (SDM) can correctly access those regions through address translation. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen

arm64: dts: intel: keembay: Always use decimal interrupts

2026-06-29T11:52:28Z

Replace the sole hexadecimal interrupt number by a decimal number, for consistency with all other interrupt numbers. Signed-off-by: Geert Uytterhoeven Signed-off-by: Dinh Nguyen

arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0

2026-06-29T11:52:28Z

Extend the gmac0 interrupt list to support 8 TX and 8 RX per-channel interrupts in addition to the combined macirq, enabling per-channel interrupt handling for improved DMA performance. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen

arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW provides clock delay

2026-05-07T12:07:22Z

The Agilex5 SoC provides RGMII TX/RX clock delay compensation through its integrated I/O hardware. Using phy-mode = "rgmii-id" instructs the MAC driver to additionally insert internal TX/RX delays, resulting in double delay being applied and causing Ethernet link timing issues. Change phy-mode to "rgmii" across all Agilex5 device tree files to reflect that the clock delay is already handled by the hardware and no additional software-inserted delay is required. Add an inline comment to satisfy checkpatch and document the hardware-provided delay. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen