<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/arm64/boot/dts, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/arm64/boot/dts?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/arm64/boot/dts?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-09-18T12:34:03Z</updated>
<entry>
<title>Merge tag 'renesas-fixes-for-v7.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes</title>
<updated>2026-09-18T12:34:03Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2026-09-18T12:33:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2d5061ff3762a71dac6809a9bd9013fd785aab28'/>
<id>urn:sha1:2d5061ff3762a71dac6809a9bd9013fd785aab28</id>
<content type='text'>
Renesas fixes for v7.3 (take two)

  - Fix UFS regression on R-Car S4.

* tag 'renesas-fixes-for-v7.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a779f0: Set UFS lane count

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'amlogic-fixes-v7.3-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes</title>
<updated>2026-09-16T11:05:33Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2026-09-16T11:05:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ce55a6545a375563983ef83eb48915a11493b64e'/>
<id>urn:sha1:ce55a6545a375563983ef83eb48915a11493b64e</id>
<content type='text'>
Amlogic DT Fixes for v7.3:
- Set of fixes for Amlogic T7:
 - use the real UART pclk
 - allow the SD card to be power cycled by dropping regulator-always-on
 - fix the pin groups of two PWM outputs
 - add the CPU cores PWM-driven supplies to fix runtime crashes
 - fix the pin groups of the vsync PWM using non-existing pin group

* tag 'amlogic-fixes-v7.3-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: amlogic: t7: fix the pin groups of the vsync PWM
  arm64: dts: amlogic: t7: khadas-vim4: add the PWM-driven supplies
  arm64: dts: amlogic: t7: fix the pin groups of two PWM outputs
  arm64: dts: amlogic: t7: khadas-vim4: allow the SD card to be power cycled
  arm64: dts: amlogic: t7: use the real UART pclk

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'renesas-fixes-for-v7.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes</title>
<updated>2026-09-14T15:01:58Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2026-09-14T15:01:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2d5adffc11cc8d694e309dc38f9a8ae7fa14a65a'/>
<id>urn:sha1:2d5adffc11cc8d694e309dc38f9a8ae7fa14a65a</id>
<content type='text'>
Renesas fixes for v7.3

  - Fix Ethernet stalls on RZ/V2H, RZ/V2N, RZ/G3E, RZ/T2H, and RZ/N2H.

* tag 'renesas-fixes-for-v7.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r9a09g087: Switch GBETH TX queue scheduling to WRR
  arm64: dts: renesas: r9a09g077: Switch GBETH TX queue scheduling to WRR
  arm64: dts: renesas: r9a09g047: Switch GBETH TX queue scheduling to WRR
  arm64: dts: renesas: r9a09g056: Switch GBETH TX queue scheduling to WRR
  arm64: dts: renesas: r9a09g057: Switch GBETH TX queue scheduling to WRR

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>arm64: dts: renesas: r8a779f0: Set UFS lane count</title>
<updated>2026-09-14T08:07:09Z</updated>
<author>
<name>Koichiro Den</name>
<email>den@valinux.co.jp</email>
</author>
<published>2026-09-11T07:30:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8dc2615d5702059b2b71fca6f93c0d7d10ae54cb'/>
<id>urn:sha1:8dc2615d5702059b2b71fca6f93c0d7d10ae54cb</id>
<content type='text'>
Since commit e72323f3b09f ("scsi: ufs: core: Configure only active lanes
during link"), the following error is observed on R-Car S4:

    ufshcd-renesas e6860000.ufs: Tx lane mismatch [config,reported] [2,1]
    ufshcd-renesas e6860000.ufs: link startup failed -67
    ufshcd-renesas e6860000.ufs: error -ENOLINK: Initialization failed with error -67
    ufshcd-renesas e6860000.ufs: probe with driver ufshcd-renesas failed with error -67

R-Car S4 has one UFS lane per direction, as described in section 152.1
of its hardware manual.  Without lanes-per-direction, the UFS platform
driver defaults to two lanes.

Previously, the core used PA_CONNECTEDRXDATALANES and
PA_CONNECTEDTXDATALANES to configure the link without checking them
against lanes-per-direction, so the missing property did not prevent
initialization.

Explicitly set lanes-per-direction to 1, now that the validation is in
place.

Fixes: 5235d551779d ("arm64: dts: renesas: r8a779f0: Add UFS node")
Cc: stable@vger.kernel.org # 7.2+
Signed-off-by: Koichiro Den &lt;den@valinux.co.jp&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Tested-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Link: https://patch.msgid.link/20260911073058.253000-1-den@valinux.co.jp
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>arm64: dts: renesas: r9a09g087: Switch GBETH TX queue scheduling to WRR</title>
<updated>2026-09-02T12:32:37Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait.rb@renesas.com</email>
</author>
<published>2026-07-22T08:53:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2ac7bad110be6ebe478d6bd57821f7f5259a1f54'/>
<id>urn:sha1:2ac7bad110be6ebe478d6bd57821f7f5259a1f54</id>
<content type='text'>
The GBETH ethernet nodes don't specify a TX scheduling policy, so stmmac
falls back to Strict Priority. In this configuration the queue with the
highest priority gets all the traffic, starving the others under load.

Under sustained UDP TX load with multiple data streams, this starvation
triggers spurious adapter resets due to TX queue timeouts:

  iperf3 -c &lt;ip&gt; -i0 -t60 --bind-dev end0 -u -b0 -P4
  end0: NETDEV WATCHDOG: CPU: 1: transmit queue 1 timed out 5228 ms
  end0: Reset adapter.

Investigation shows that only the highest priority queue is advancing
while the others stall for more than 5 seconds, causing a netdev watchdog
reset.

Switch the TX scheduling policy to Weighted-Round-Robin (WRR) so that
traffic is processed across all queues, eliminating the stalls.

Fixes: c4698a34993b ("arm64: dts: renesas: r9a09g087: Add GMAC nodes")
Signed-off-by: Ovidiu Panait &lt;ovidiu.panait.rb@renesas.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Link: https://patch.msgid.link/20260722085353.136986-6-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>arm64: dts: renesas: r9a09g077: Switch GBETH TX queue scheduling to WRR</title>
<updated>2026-09-02T12:32:37Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait.rb@renesas.com</email>
</author>
<published>2026-07-22T08:53:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f9d9a1913c09366bf7b967d39575e06cb80128dc'/>
<id>urn:sha1:f9d9a1913c09366bf7b967d39575e06cb80128dc</id>
<content type='text'>
The GBETH ethernet nodes don't specify a TX scheduling policy, so stmmac
falls back to Strict Priority. In this configuration the queue with the
highest priority gets all the traffic, starving the others under load.

Under sustained UDP TX load with multiple data streams, this starvation
triggers spurious adapter resets due to TX queue timeouts:

  iperf3 -c &lt;ip&gt; -i0 -t60 --bind-dev end0 -u -b0 -P4
  end0: NETDEV WATCHDOG: CPU: 1: transmit queue 1 timed out 5228 ms
  end0: Reset adapter.

Investigation shows that only the highest priority queue is advancing
while the others stall for more than 5 seconds, causing a netdev watchdog
reset.

Switch the TX scheduling policy to Weighted-Round-Robin (WRR) so that
traffic is processed across all queues, eliminating the stalls.

Fixes: 394c1e24a4cf ("arm64: dts: renesas: r9a09g077: Add GMAC nodes")
Signed-off-by: Ovidiu Panait &lt;ovidiu.panait.rb@renesas.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Link: https://patch.msgid.link/20260722085353.136986-5-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>arm64: dts: renesas: r9a09g047: Switch GBETH TX queue scheduling to WRR</title>
<updated>2026-09-02T12:32:37Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait.rb@renesas.com</email>
</author>
<published>2026-07-22T08:53:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=63016c3a91f2c458ca75869c8c782e899591f22d'/>
<id>urn:sha1:63016c3a91f2c458ca75869c8c782e899591f22d</id>
<content type='text'>
The GBETH ethernet nodes don't specify a TX scheduling policy, so stmmac
falls back to Strict Priority. In this configuration the queue with the
highest priority gets all the traffic, starving the others under load.

Under sustained UDP TX load with multiple data streams, this starvation
triggers spurious adapter resets due to TX queue timeouts:

  iperf3 -c &lt;ip&gt; -i0 -t60 --bind-dev end0 -u -b0 -P4
  end0: NETDEV WATCHDOG: CPU: 1: transmit queue 1 timed out 5228 ms
  end0: Reset adapter.

Investigation shows that only the highest priority queue is advancing
while the others stall for more than 5 seconds, causing a netdev watchdog
reset.

Switch the TX scheduling policy to Weighted-Round-Robin (WRR) so that
traffic is processed across all queues, eliminating the stalls.

Fixes: 41ffbb1c42d3 ("arm64: dts: renesas: r9a09g047: Add GBETH nodes")
Signed-off-by: Ovidiu Panait &lt;ovidiu.panait.rb@renesas.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Tested-by: Tommaso Merciai &lt;tommaso.merciai.xr@bp.renesas.com&gt;
Link: https://patch.msgid.link/20260722085353.136986-4-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>arm64: dts: renesas: r9a09g056: Switch GBETH TX queue scheduling to WRR</title>
<updated>2026-09-02T12:32:37Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait.rb@renesas.com</email>
</author>
<published>2026-07-22T08:53:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=66fcbdbeca0118b8aeac218b33fa18c394513543'/>
<id>urn:sha1:66fcbdbeca0118b8aeac218b33fa18c394513543</id>
<content type='text'>
The GBETH ethernet nodes don't specify a TX scheduling policy, so stmmac
falls back to Strict Priority. In this configuration the queue with the
highest priority gets all the traffic, starving the others under load.

Under sustained UDP TX load with multiple data streams, this starvation
triggers spurious adapter resets due to TX queue timeouts:

  iperf3 -c &lt;ip&gt; -i0 -t60 --bind-dev end0 -u -b0 -P4
  end0: NETDEV WATCHDOG: CPU: 1: transmit queue 1 timed out 5228 ms
  end0: Reset adapter.

Investigation shows that only the highest priority queue is advancing
while the others stall for more than 5 seconds, causing a netdev watchdog
reset.

Switch the TX scheduling policy to Weighted-Round-Robin (WRR) so that
traffic is processed across all queues, eliminating the stalls.

Fixes: c8c8a57c5b40 ("arm64: dts: renesas: r9a09g056: Add GBETH nodes")
Signed-off-by: Ovidiu Panait &lt;ovidiu.panait.rb@renesas.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Link: https://patch.msgid.link/20260722085353.136986-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>arm64: dts: renesas: r9a09g057: Switch GBETH TX queue scheduling to WRR</title>
<updated>2026-09-02T12:32:37Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait.rb@renesas.com</email>
</author>
<published>2026-07-22T08:53:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=33da68f61d25ef8411489d06514ff627c1f88152'/>
<id>urn:sha1:33da68f61d25ef8411489d06514ff627c1f88152</id>
<content type='text'>
The GBETH ethernet nodes don't specify a TX scheduling policy, so stmmac
falls back to Strict Priority. In this configuration the queue with the
highest priority gets all the traffic, starving the others under load.

Under sustained UDP TX load with multiple data streams, this starvation
triggers spurious adapter resets due to TX queue timeouts:

  iperf3 -c &lt;ip&gt; -i0 -t60 --bind-dev end0 -u -b0 -P4
  end0: NETDEV WATCHDOG: CPU: 1: transmit queue 1 timed out 5228 ms
  end0: Reset adapter.

Investigation shows that only the highest priority queue is advancing
while the others stall for more than 5 seconds, causing a netdev watchdog
reset.

Switch the TX scheduling policy to Weighted-Round-Robin (WRR) so that
traffic is processed across all queues, eliminating the stalls.

Fixes: 050ee38d0002 ("arm64: dts: renesas: r9a09g057: Add GBETH nodes")
Signed-off-by: Ovidiu Panait &lt;ovidiu.panait.rb@renesas.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Link: https://patch.msgid.link/20260722085353.136986-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>arm64: dts: socfpga: change access permission from 755 to 644</title>
<updated>2026-08-31T23:08:36Z</updated>
<author>
<name>Dinh Nguyen</name>
<email>dinguyen@kernel.org</email>
</author>
<published>2026-08-28T02:31:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5f8cb07d7a8573753c5d31dc76b51cab8e5e9460'/>
<id>urn:sha1:5f8cb07d7a8573753c5d31dc76b51cab8e5e9460</id>
<content type='text'>
These files have an incorrect access permission of 755 instead of 644.
Change them to the correct access permission of 644.

Fixes: 4bc04eb90b7c ("arm64: dts: socfpga: stratix10: Add emmc support")
Cc: &lt;stable@vger.kernel.org&gt; # v7.1+
Signed-off-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
</entry>
</feed>
