<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/arm64/include/asm/kvm_host.h, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/arm64/include/asm/kvm_host.h?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/arm64/include/asm/kvm_host.h?h=jd%2Forphan-parallel'/>
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<updated>2020-09-30T13:05:35Z</updated>
<entry>
<title>Merge branch 'kvm-arm64/hyp-pcpu' into kvmarm-master/next</title>
<updated>2020-09-30T13:05:35Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-30T13:05:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=14ef9d04928b61d699fd0dd858b14b5d8150113e'/>
<id>urn:sha1:14ef9d04928b61d699fd0dd858b14b5d8150113e</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'arm64/for-next/ghostbusters' into kvm-arm64/hyp-pcpu</title>
<updated>2020-09-30T08:48:30Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-30T08:48:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=816c347f3a48fb15370b23664760ea61286fea05'/>
<id>urn:sha1:816c347f3a48fb15370b23664760ea61286fea05</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>kvm: arm64: Create separate instances of kvm_host_data for VHE/nVHE</title>
<updated>2020-09-30T07:37:13Z</updated>
<author>
<name>David Brazdil</name>
<email>dbrazdil@google.com</email>
</author>
<published>2020-09-22T20:49:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2a1198c9b436402582f7beed57028044b819329c'/>
<id>urn:sha1:2a1198c9b436402582f7beed57028044b819329c</id>
<content type='text'>
Host CPU context is stored in a global per-cpu variable `kvm_host_data`.
In preparation for introducing independent per-CPU region for nVHE hyp,
create two separate instances of `kvm_host_data`, one for VHE and one
for nVHE.

Signed-off-by: David Brazdil &lt;dbrazdil@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Link: https://lore.kernel.org/r/20200922204910.7265-9-dbrazdil@google.com
</content>
</entry>
<entry>
<title>KVM: arm64: Get rid of kvm_arm_have_ssbd()</title>
<updated>2020-09-29T15:08:17Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-18T12:59:32Z</published>
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<id>urn:sha1:7311467702710cc30ac4e3a6c6670a766e7667f9</id>
<content type='text'>
kvm_arm_have_ssbd() is now completely unused, get rid of it.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>arm64: Rewrite Spectre-v2 mitigation code</title>
<updated>2020-09-29T15:08:15Z</updated>
<author>
<name>Will Deacon</name>
<email>will@kernel.org</email>
</author>
<published>2020-09-15T22:30:17Z</published>
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<id>urn:sha1:d4647f0a2ad711101067cba69c34716758aa1e48</id>
<content type='text'>
The Spectre-v2 mitigation code is pretty unwieldy and hard to maintain.
This is largely due to it being written hastily, without much clue as to
how things would pan out, and also because it ends up mixing policy and
state in such a way that it is very difficult to figure out what's going
on.

Rewrite the Spectre-v2 mitigation so that it clearly separates state from
policy and follows a more structured approach to handling the mitigation.

Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'kvm-arm64/pmu-5.9' into kvmarm-master/next</title>
<updated>2020-09-29T14:12:54Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-29T14:12:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2e02cbb236d6ac12e04629f94b7032a94f968165'/>
<id>urn:sha1:2e02cbb236d6ac12e04629f94b7032a94f968165</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Add PMU event filtering infrastructure</title>
<updated>2020-09-29T13:19:39Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-02-12T11:31:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d7eec2360e389cc877a76c2b098f7b745007d2b2'/>
<id>urn:sha1:d7eec2360e389cc877a76c2b098f7b745007d2b2</id>
<content type='text'>
It can be desirable to expose a PMU to a guest, and yet not want the
guest to be able to count some of the implemented events (because this
would give information on shared resources, for example.

For this, let's extend the PMUv3 device API, and offer a way to setup a
bitmap of the allowed events (the default being no bitmap, and thus no
filtering).

Userspace can thus allow/deny ranges of event. The default policy
depends on the "polarity" of the first filter setup (default deny if the
filter allows events, and default allow if the filter denies events).
This allows to setup exactly what is allowed for a given guest.

Note that although the ioctl is per-vcpu, the map of allowed events is
global to the VM (it can be setup from any vcpu until the vcpu PMU is
initialized).

Reviewed-by: Andrew Jones &lt;drjones@redhat.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Use event mask matching architecture revision</title>
<updated>2020-09-29T13:19:38Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-03-17T11:11:56Z</published>
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<id>urn:sha1:fd65a3b5f855c37167890d86e261a20bab1a14a4</id>
<content type='text'>
The PMU code suffers from a small defect where we assume that the event
number provided by the guest is always 16 bit wide, even if the CPU only
implements the ARMv8.0 architecture. This isn't really problematic in
the sense that the event number ends up in a system register, cropping
it to the right width, but still this needs fixing.

In order to make it work, let's probe the version of the PMU that the
guest is going to use. This is done by temporarily creating a kernel
event and looking at the PMUVer field that has been saved at probe time
in the associated arm_pmu structure. This in turn gets saved in the kvm
structure, and subsequently used to compute the event mask that gets
used throughout the PMU code.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'kvm-arm64/nvhe-hyp-context' into kvmarm-master/next</title>
<updated>2020-09-16T09:59:17Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-16T09:59:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=81867b75dbfde82fda5476c7c219a777aa36fbaf'/>
<id>urn:sha1:81867b75dbfde82fda5476c7c219a777aa36fbaf</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: nVHE: Migrate hyp-init to SMCCC</title>
<updated>2020-09-15T17:39:04Z</updated>
<author>
<name>Andrew Scull</name>
<email>ascull@google.com</email>
</author>
<published>2020-09-15T10:46:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=04e4caa8d355d19fd7d26734bd2b9e3b563bb22a'/>
<id>urn:sha1:04e4caa8d355d19fd7d26734bd2b9e3b563bb22a</id>
<content type='text'>
To complete the transition to SMCCC, the hyp initialization is given a
function ID. This looks neater than comparing the hyp stub function IDs
to the page table physical address.

Some care is taken to only clobber x0-3 before the host context is saved
as only those registers can be clobbered accoring to SMCCC. Fortunately,
only a few acrobatics are needed. The possible new tpidr_el2 is moved to
the argument in x2 so that it can be stashed in tpidr_el2 early to free
up a scratch register. The page table configuration then makes use of
x0-2.

Signed-off-by: Andrew Scull &lt;ascull@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20200915104643.2543892-19-ascull@google.com
</content>
</entry>
</feed>
