wireguard-linux/arch/arm64/include/uapi/asm/hwcap.h, branch jd/orphan-parallel

arm64: mte: CPU feature detection and initial sysreg configuration

2020-09-03T16:26:32Z

Add the cpufeature and hwcap entries to detect the presence of MTE. Any secondary CPU not supporting the feature, if detected on the boot CPU, will be parked. Add the minimum SCTLR_EL1 and HCR_EL2 bits for enabling MTE. The Normal Tagged memory type is configured in MAIR_EL1 before the MMU is enabled in order to avoid disrupting other CPUs in the CnP domain. Signed-off-by: Vincenzo Frascino Co-developed-by: Catalin Marinas Signed-off-by: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose

arm64: Reserve HWCAP2_MTE as (1 << 18)

2020-07-24T10:55:29Z

While MTE is not supported in the upstream kernel yet, add a comment that HWCAP2_MTE as (1 << 18) is reserved. Glibc makes use of it for the resolving (ifunc) of the MTE-safe string routines. Signed-off-by: Catalin Marinas

arm64: Basic Branch Target Identification support

2020-03-16T17:19:48Z

This patch adds the bare minimum required to expose the ARMv8.5 Branch Target Identification feature to userspace. By itself, this does _not_ automatically enable BTI for any initial executable pages mapped by execve(). This will come later, but for now it should be possible to enable BTI manually on those pages by using mprotect() from within the target process. Other arches already using the generic mman.h are already using 0x10 for arch-specific prot flags, so we use that for PROT_BTI here. For consistency, signal handler entry points in BTI guarded pages are required to be annotated as such, just like any other function. This blocks a relatively minor attack vector, but comforming userspace will have the annotations anyway, so we may as well enforce them. Signed-off-by: Mark Brown Signed-off-by: Dave Martin Reviewed-by: Catalin Marinas Signed-off-by: Catalin Marinas

Merge branch 'for-next/rng' into for-next/core

2020-01-22T11:38:53Z

* for-next/rng: (2 commits) arm64: Use v8.5-RNG entropy for KASLR seed ...

arm64: Implement archrandom.h for ARMv8.5-RNG

2020-01-22T09:54:18Z

Expose the ID_AA64ISAR0.RNDR field to userspace, as the RNG system registers are always available at EL0. Implement arch_get_random_seed_long using RNDR. Given that the TRNG is likely to be a shared resource between cores, and VMs, do not explicitly force re-seeding with RNDRRS. In order to avoid code complexity and potential issues with hetrogenous systems only provide values after cpufeature has finalized the system capabilities. Signed-off-by: Richard Henderson [Modified to only function after cpufeature has finalized the system capabilities and move all the code into the header -- broonie] Signed-off-by: Mark Brown Reviewed-by: Mark Rutland Reviewed-by: Ard Biesheuvel [will: Advertise HWCAP via /proc/cpuinfo] Signed-off-by: Will Deacon

arm64: cpufeature: Export matrix and other features to userspace

2020-01-15T11:13:07Z

Export the features introduced as part of ARMv8.6 exposed in the ID_AA64ISAR1_EL1 and ID_AA64ZFR0_EL1 registers. This introduces the Matrix features (ARMv8.2-I8MM, ARMv8.2-F64MM and ARMv8.2-F32MM) along with BFloat16 (Armv8.2-BF16), speculation invalidation (SPECRES) and Data Gathering Hint (ARMv8.0-DGH). Signed-off-by: Julien Grall [Added other features in those registers] Signed-off-by: Steven Price [will: Don't advertise SPECRES to userspace] Signed-off-by: Will Deacon

arm64: Expose FRINT capabilities to userspace

2019-06-25T13:24:00Z

ARMv8.5 introduces the FRINT series of instructions for rounding floating point numbers to integers. Provide a capability to userspace in order to allow applications to determine if the system supports these instructions. Signed-off-by: Mark Brown Acked-by: Will Deacon Signed-off-by: Catalin Marinas

arm64: Expose ARMv8.5 CondM capability to userspace

2019-06-25T13:21:41Z

ARMv8.5 adds new instructions XAFLAG and AXFLAG to translate the representation of the results of floating point comparisons between the native ARM format and an alternative format used by some software. Add a hwcap allowing userspace to determine if they are present, since we referred to earlier CondM extensions as FLAGM call these extensions FLAGM2. Signed-off-by: Mark Brown Acked-by: Will Deacon Signed-off-by: Catalin Marinas

arm64: Expose SVE2 features for userspace

2019-04-23T17:02:00Z

This patch provides support for reporting the presence of SVE2 and its optional features to userspace. This will also enable visibility of SVE2 for guests, when KVM support for SVE-enabled guests is available. Signed-off-by: Dave Martin Signed-off-by: Will Deacon

arm64: Expose DC CVADP to userspace

2019-04-16T15:27:56Z

ARMv8.5 builds upon the ARMv8.2 DC CVAP instruction by introducing a DC CVADP instruction which cleans the data cache to the point of deep persistence. Let's expose this support via the arm64 ELF hwcaps. Signed-off-by: Andrew Murray Reviewed-by: Dave Martin Signed-off-by: Will Deacon