<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/arm64/kvm/hyp, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/arm64/kvm/hyp?h=jd%2Forphan-parallel</id>
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<updated>2020-10-21T22:05:58Z</updated>
<entry>
<title>Merge branch 'kvm-fixes' into 'next'</title>
<updated>2020-10-21T22:05:58Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2020-10-21T22:05:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c0623f5e5d21d65d08f6276ca4e64d470c833761'/>
<id>urn:sha1:c0623f5e5d21d65d08f6276ca4e64d470c833761</id>
<content type='text'>
Pick up bugfixes from 5.9, otherwise various tests fail.
</content>
</entry>
<entry>
<title>Merge tag 'kvmarm-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD</title>
<updated>2020-10-20T12:14:25Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2020-10-20T12:14:25Z</published>
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<id>urn:sha1:1b21c8db0e3b71523ada0cf568372ebfcf0d3466</id>
<content type='text'>
KVM/arm64 updates for Linux 5.10

- New page table code for both hypervisor and guest stage-2
- Introduction of a new EL2-private host context
- Allow EL2 to have its own private per-CPU variables
- Support of PMU event filtering
- Complete rework of the Spectre mitigation
</content>
</entry>
<entry>
<title>Merge branches 'kvm-arm64/pt-new' and 'kvm-arm64/pmu-5.9' into kvmarm-master/next</title>
<updated>2020-10-02T08:25:55Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-10-02T08:25:55Z</published>
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<id>urn:sha1:4e5dc64c43192b4fd4c96ac150a8f013065f5f5b</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: Pass level hint to TLBI during stage-2 permission fault</title>
<updated>2020-10-02T08:16:07Z</updated>
<author>
<name>Will Deacon</name>
<email>will@kernel.org</email>
</author>
<published>2020-09-30T13:18:01Z</published>
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<id>urn:sha1:b259d137e91d80bf92eac453ffab179eb7941ede</id>
<content type='text'>
Alex pointed out that we don't pass a level hint to the TLBI instruction
when handling a stage-2 permission fault, even though the walker does
at some point have the level information in its hands.

Rework stage2_update_leaf_attrs() so that it can optionally return the
level of the updated pte to its caller, which can in turn be used to
provide the correct TLBI level hint.

Reported-by: Alexandru Elisei &lt;alexandru.elisei@arm.com&gt;
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Reviewed-by: Alexandru Elisei &lt;alexandru.elisei@arm.com&gt;
Reviewed-by: Gavin Shan &lt;gshan@redhat.com&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/595cc73e-636e-8b3a-f93a-b4e9fb218db8@arm.com
Link: https://lore.kernel.org/r/20200930131801.16889-1-will@kernel.org
</content>
</entry>
<entry>
<title>KVM: arm64: Restore missing ISB on nVHE __tlb_switch_to_guest</title>
<updated>2020-10-01T08:53:45Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-07-13T14:15:14Z</published>
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<id>urn:sha1:452d62227958e149e5c7b0084a559c0957c3ff2a</id>
<content type='text'>
Commit a0e50aa3f4a8 ("KVM: arm64: Factor out stage 2 page table
data from struct kvm") dropped the ISB after __load_guest_stage2(),
only leaving the one that is required when the speculative AT
workaround is in effect.

As Andrew points it: "This alternative is 'backwards' to avoid a
double ISB as there is one in __load_guest_stage2 when the workaround
is active."

Restore the missing ISB, conditionned on the AT workaround not being
active.

Fixes: a0e50aa3f4a8 ("KVM: arm64: Factor out stage 2 page table data from struct kvm")
Reported-by: Andrew Scull &lt;ascull@google.com&gt;
Reported-by: Thomas Tai &lt;thomas.tai@oracle.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'kvm-arm64/hyp-pcpu' into kvmarm-master/next</title>
<updated>2020-09-30T13:05:35Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-30T13:05:35Z</published>
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<id>urn:sha1:14ef9d04928b61d699fd0dd858b14b5d8150113e</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'arm64/for-next/ghostbusters' into kvm-arm64/hyp-pcpu</title>
<updated>2020-09-30T08:48:30Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2020-09-30T08:48:30Z</published>
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<id>urn:sha1:816c347f3a48fb15370b23664760ea61286fea05</id>
<content type='text'>
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>kvm: arm64: Set up hyp percpu data for nVHE</title>
<updated>2020-09-30T07:37:14Z</updated>
<author>
<name>David Brazdil</name>
<email>dbrazdil@google.com</email>
</author>
<published>2020-09-22T20:49:09Z</published>
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<id>urn:sha1:30c953911c4370bfb622ee1c2fcc7e78c84df800</id>
<content type='text'>
Add hyp percpu section to linker script and rename the corresponding ELF
sections of hyp/nvhe object files. This moves all nVHE-specific percpu
variables to the new hyp percpu section.

Allocate sufficient amount of memory for all percpu hyp regions at global KVM
init time and create corresponding hyp mappings.

The base addresses of hyp percpu regions are kept in a dynamically allocated
array in the kernel.

Add NULL checks in PMU event-reset code as it may run before KVM memory is
initialized.

Signed-off-by: David Brazdil &lt;dbrazdil@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Link: https://lore.kernel.org/r/20200922204910.7265-10-dbrazdil@google.com
</content>
</entry>
<entry>
<title>kvm: arm64: Create separate instances of kvm_host_data for VHE/nVHE</title>
<updated>2020-09-30T07:37:13Z</updated>
<author>
<name>David Brazdil</name>
<email>dbrazdil@google.com</email>
</author>
<published>2020-09-22T20:49:08Z</published>
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<id>urn:sha1:2a1198c9b436402582f7beed57028044b819329c</id>
<content type='text'>
Host CPU context is stored in a global per-cpu variable `kvm_host_data`.
In preparation for introducing independent per-CPU region for nVHE hyp,
create two separate instances of `kvm_host_data`, one for VHE and one
for nVHE.

Signed-off-by: David Brazdil &lt;dbrazdil@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Link: https://lore.kernel.org/r/20200922204910.7265-9-dbrazdil@google.com
</content>
</entry>
<entry>
<title>kvm: arm64: Duplicate arm64_ssbd_callback_required for nVHE hyp</title>
<updated>2020-09-30T07:37:13Z</updated>
<author>
<name>David Brazdil</name>
<email>dbrazdil@google.com</email>
</author>
<published>2020-09-22T20:49:07Z</published>
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<id>urn:sha1:df4c8214a18d202fa0ec221a001f640e020f7e44</id>
<content type='text'>
Hyp keeps track of which cores require SSBD callback by accessing a
kernel-proper global variable. Create an nVHE symbol of the same name
and copy the value from kernel proper to nVHE as KVM is being enabled
on a core.

Done in preparation for separating percpu memory owned by kernel
proper and nVHE.

Signed-off-by: David Brazdil &lt;dbrazdil@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Link: https://lore.kernel.org/r/20200922204910.7265-8-dbrazdil@google.com
</content>
</entry>
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