wireguard-linux/arch/csky/abiv2, branch jd/unified-crypt-queue

csky: Fixup cpu speculative execution to IO area

2020-04-03T04:40:07Z

For the memory size ( > 512MB, < 1GB), the MSA setting is: - SSEG0: PHY_START , PHY_START + 512MB - SSEG1: PHY_START + 512MB, PHY_START + 1GB But the real memory is no more than 1GB, there is a gap between the end size of memory and border of 1GB. CPU could speculatively execute to that gap and if the gap of the bus couldn't respond to the CPU request, then the crash will happen. Now make the setting with: - SSEG0: PHY_START , PHY_START + 512MB (no change) - SSEG1: Disabled (We use highmem to use the memory of 512MB~1GB) We also deprecated zhole_szie[] settings, it's only used by arm style CPUs. All memory gap should use Reserved setting of dts in csky system. Signed-off-by: Guo Ren

csky: Implement ftrace with regs

2020-03-08T12:55:14Z

This patch implements FTRACE_WITH_REGS for csky, which allows a traced function's arguments (and some other registers) to be captured into a struct pt_regs, allowing these to be inspected and/or modified. Signed-off-by: Guo Ren

csky: Fixup init_fpu compile warning with __init

2020-03-08T12:55:14Z

WARNING: vmlinux.o(.text+0x2366): Section mismatch in reference from the function csky_start_secondary() to the function .init.text:init_fpu() The function csky_start_secondary() references the function __init init_fpu(). This is often because csky_start_secondary lacks a __init annotation or the annotation of init_fpu is wrong. Reported-by: Lu Chongzhi Signed-off-by: Guo Ren

csky: Add flush_icache_mm to defer flush icache all

2020-02-21T07:43:24Z

Some CPUs don't support icache.va instruction to maintain the whole smp cores' icache. Using icache.all + IPI casue a lot on performace and using defer mechanism could reduce the number of calling icache _flush_all functions. Signed-off-by: Guo Ren

csky: Optimize abiv2 copy_to_user_page with VM_EXEC

2020-02-21T07:43:24Z

Only when vma is for VM_EXEC, we need sync dcache & icache. eg: - gdb ptrace modify user space instruction code area. Add VM_EXEC condition to reduce unnecessary cache flush. The abiv1 cpus' cache are all VIPT, so we still need to deal with dcache aliasing problem. But there is optimized way to use cache color, just like what's done in arch/csky/abiv1/inc/abi/page.h. Signed-off-by: Guo Ren

csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)

2020-02-21T07:43:24Z

Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache. As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache(). Signed-off-by: Guo Ren

csky: Remove unnecessary flush_icache_* implementation

2020-02-21T07:43:24Z

The abiv2 CPUs are all PIPT cache, so there is no need to implement flush_icache_page function. The function flush_icache_user_range hasn't been used, so just remove it. The function flush_cache_range is not necessary for PIPT cache when tlb mapping changed. Signed-off-by: Guo Ren

csky: Set regs->usp to kernel sp, when the exception is from kernel

2020-02-21T07:43:24Z

In the past, we didn't care about kernel sp when saving pt_reg. But in some cases, we still need pt_reg->usp to represent the kernel stack before enter exception. For cmpxhg in atomic.S, we need save and restore usp for above. Signed-off-by: Guo Ren

Merge tag 'csky-for-linus-5.3-rc1' of git://github.com/c-sky/csky-linux

2019-07-19T19:15:33Z

Pull arch/csky pupdates from Guo Ren: "This round of csky subsystem gives two features (ASID algorithm update, Perf pmu record support) and some fixups. ASID updates: - Revert mmu ASID mechanism - Add new asid lib code from arm - Use generic asid algorithm to implement switch_mm - Improve tlb operation with help of asid Perf pmu record support: - Init pmu as a device - Add count-width property for csky pmu - Add pmu interrupt support - Fix perf record in kernel/user space - dt-bindings: Add csky PMU bindings Fixes: - Fixup no panic in kernel for some traps - Fixup some error count in 810 & 860. - Fixup abiv1 memset error" * tag 'csky-for-linus-5.3-rc1' of git://github.com/c-sky/csky-linux: csky: Fixup abiv1 memset error csky: Improve tlb operation with help of asid csky: Use generic asid algorithm to implement switch_mm csky: Add new asid lib code from arm csky: Revert mmu ASID mechanism dt-bindings: csky: Add csky PMU bindings dt-bindings: interrupt-controller: Update csky mpintc csky: Fixup some error count in 810 & 860. csky: Fix perf record in kernel/user space csky: Add pmu interrupt support csky: Add count-width property for csky pmu csky: Init pmu as a device csky: Fixup no panic in kernel for some traps csky: Select intc & timer drivers

csky: Use generic asid algorithm to implement switch_mm

2019-07-19T06:21:36Z

Use linux generic asid/vmid algorithm to implement csky switch_mm function. The algorithm is from arm and it could work with SMP system. It'll help reduce tlb flush for switch_mm in task/vm switch. Signed-off-by: Guo Ren Cc: Arnd Bergmann