<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/csky/kernel/traps.c, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/csky/kernel/traps.c?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/csky/kernel/traps.c?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-03T03:37:51Z</updated>
<entry>
<title>csky: Add uprobes support</title>
<updated>2020-04-03T03:37:51Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2020-04-02T11:52:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8f6bb793b2be82f1f73bfb416486f156f70b4314'/>
<id>urn:sha1:8f6bb793b2be82f1f73bfb416486f156f70b4314</id>
<content type='text'>
This patch adds support for uprobes on csky architecture.

Just like kprobe, it support single-step and simulate instructions.

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
</content>
</entry>
<entry>
<title>csky: Add kprobes supported</title>
<updated>2020-04-03T03:14:17Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2020-04-01T01:17:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=33e53ae1ce413a081254e686d9b27cc1b3585e2f'/>
<id>urn:sha1:33e53ae1ce413a081254e686d9b27cc1b3585e2f</id>
<content type='text'>
This patch enable kprobes, kretprobes, ftrace interface. It utilized
software breakpoint and single step debug exceptions, instructions
simulation on csky.

We use USR_BKPT replace origin instruction, and the kprobe handler
prepares an excutable memory slot for out-of-line execution with a
copy of the original instruction being probed. Most of instructions
could be executed by single-step, but some instructions need origin
pc value to execute and we need software simulate these instructions.

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
</content>
</entry>
<entry>
<title>csky: Fixup get wrong psr value from phyical reg</title>
<updated>2020-03-31T16:06:40Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2020-03-31T15:45:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9c0e343d7654a329d1f9b53d253cbf7fb6eff85d'/>
<id>urn:sha1:9c0e343d7654a329d1f9b53d253cbf7fb6eff85d</id>
<content type='text'>
We should get psr value from regs-&gt;psr in stack, not directly get
it from phyiscal register then save the vector number in
tsk-&gt;trap_no.

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'csky-for-linus-5.3-rc1' of git://github.com/c-sky/csky-linux</title>
<updated>2019-07-19T19:15:33Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-07-19T19:15:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a84d2d2906f983fb80f5dcc3e8e7c3ad70aa9f0d'/>
<id>urn:sha1:a84d2d2906f983fb80f5dcc3e8e7c3ad70aa9f0d</id>
<content type='text'>
Pull arch/csky pupdates from Guo Ren:
 "This round of csky subsystem gives two features (ASID algorithm
  update, Perf pmu record support) and some fixups.

  ASID updates:
   - Revert mmu ASID mechanism
   - Add new asid lib code from arm
   - Use generic asid algorithm to implement switch_mm
   - Improve tlb operation with help of asid

  Perf pmu record support:
   - Init pmu as a device
   - Add count-width property for csky pmu
   - Add pmu interrupt support
   - Fix perf record in kernel/user space
   - dt-bindings: Add csky PMU bindings

  Fixes:
   - Fixup no panic in kernel for some traps
   - Fixup some error count in 810 &amp; 860.
   - Fixup abiv1 memset error"

* tag 'csky-for-linus-5.3-rc1' of git://github.com/c-sky/csky-linux:
  csky: Fixup abiv1 memset error
  csky: Improve tlb operation with help of asid
  csky: Use generic asid algorithm to implement switch_mm
  csky: Add new asid lib code from arm
  csky: Revert mmu ASID mechanism
  dt-bindings: csky: Add csky PMU bindings
  dt-bindings: interrupt-controller: Update csky mpintc
  csky: Fixup some error count in 810 &amp; 860.
  csky: Fix perf record in kernel/user space
  csky: Add pmu interrupt support
  csky: Add count-width property for csky pmu
  csky: Init pmu as a device
  csky: Fixup no panic in kernel for some traps
  csky: Select intc &amp; timer drivers
</content>
</entry>
<entry>
<title>csky: Fixup no panic in kernel for some traps</title>
<updated>2019-07-19T06:21:36Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2019-05-10T09:07:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3158d28953fcd85492b28b1d2d5a5e20bb62a626'/>
<id>urn:sha1:3158d28953fcd85492b28b1d2d5a5e20bb62a626</id>
<content type='text'>
These traps couldn't be hanppen in kernel and we must panic there not
send a signal to userspace.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>signal: Remove the task parameter from force_sig_fault</title>
<updated>2019-05-29T14:31:43Z</updated>
<author>
<name>Eric W. Biederman</name>
<email>ebiederm@xmission.com</email>
</author>
<published>2019-05-23T16:04:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2e1661d2673667d886cd40ad9f414cb6db48d8da'/>
<id>urn:sha1:2e1661d2673667d886cd40ad9f414cb6db48d8da</id>
<content type='text'>
As synchronous exceptions really only make sense against the current
task (otherwise how are you synchronous) remove the task parameter
from from force_sig_fault to make it explicit that is what is going
on.

The two known exceptions that deliver a synchronous exception to a
stopped ptraced task have already been changed to
force_sig_fault_to_task.

The callers have been changed with the following emacs regular expression
(with obvious variations on the architectures that take more arguments)
to avoid typos:

force_sig_fault[(]\([^,]+\)[,]\([^,]+\)[,]\([^,]+\)[,]\W+current[)]
-&gt;
force_sig_fault(\1,\2,\3)

Signed-off-by: "Eric W. Biederman" &lt;ebiederm@xmission.com&gt;
</content>
</entry>
<entry>
<title>csky: remove unused members in processor.h</title>
<updated>2018-12-31T15:16:00Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-12-09T09:31:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=17a68777bc883c8044c8b2d40aa112ff4e8a4fb1'/>
<id>urn:sha1:17a68777bc883c8044c8b2d40aa112ff4e8a4fb1</id>
<content type='text'>
Cleanup struct cpuinfo_csky and struct thread_struct, remove all esp0
related code. We could get pt_regs from sp and backtrace could use fp
in switch_stack.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
</content>
</entry>
<entry>
<title>csky: Exception handling and mm-fault</title>
<updated>2018-10-25T15:36:19Z</updated>
<author>
<name>Guo Ren</name>
<email>ren_guo@c-sky.com</email>
</author>
<published>2018-09-05T06:25:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=081860b970adb69888734df0c8aa849b00ea7254'/>
<id>urn:sha1:081860b970adb69888734df0c8aa849b00ea7254</id>
<content type='text'>
This patch adds exception handling code, cpuinfo and mm-fault code.

Signed-off-by: Guo Ren &lt;ren_guo@c-sky.com&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
</feed>
