<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/mips/mm, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/mips/mm?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/mips/mm?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-10-16T19:40:55Z</updated>
<entry>
<title>Merge tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2020-10-16T19:40:55Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-10-16T19:40:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=09a31a7e3723afd79022d5d3ff3634c2630c2eeb'/>
<id>urn:sha1:09a31a7e3723afd79022d5d3ff3634c2630c2eeb</id>
<content type='text'>
Pull MIPS updates from Thomas Bogendoerfer:

 - removed support for PNX833x alias NXT_STB22x

 - included Ingenic SoC support into generic MIPS kernels

 - added support for new Ingenic SoCs

 - converted workaround selection to use Kconfig

 - replaced old boot mem functions by memblock_*

 - enabled COP2 usage in kernel for Loongson64 to make use
   of 16byte load/stores possible

 - cleanups and fixes

* tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (92 commits)
  MIPS: DEC: Restore bootmem reservation for firmware working memory area
  MIPS: dec: fix section mismatch
  bcm963xx_tag.h: fix duplicated word
  mips: ralink: enable zboot support
  MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES
  MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit
  MIPS: cpu-probe: introduce exclusive R3k CPU probe
  MIPS: cpu-probe: move fpu probing/handling into its own file
  MIPS: replace add_memory_region with memblock
  MIPS: Loongson64: Clean up numa.c
  MIPS: Loongson64: Select SMP in Kconfig to avoid build error
  mips: octeon: Add Ubiquiti E200 and E220 boards
  MIPS: SGI-IP28: disable use of ll/sc in kernel
  MIPS: tx49xx: move tx4939_add_memory_regions into only user
  MIPS: pgtable: Remove used PAGE_USERIO define
  MIPS: alchemy: Share prom_init implementation
  MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabled
  MIPS: process: include exec.h header in process.c
  MIPS: process: Add prototype for function arch_dup_task_struct
  MIPS: idle: Add prototype for function check_wait
  ...
</content>
</entry>
<entry>
<title>dma-mapping: merge &lt;linux/dma-noncoherent.h&gt; into &lt;linux/dma-map-ops.h&gt;</title>
<updated>2020-10-06T05:07:06Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-09-22T13:36:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9f4df96b8781e40d0cb0e32eb3d1f6d87375adf9'/>
<id>urn:sha1:9f4df96b8781e40d0cb0e32eb3d1f6d87375adf9</id>
<content type='text'>
Move more nitty gritty DMA implementation details into the common
internal header.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>dma-mapping: merge &lt;linux/dma-contiguous.h&gt; into &lt;linux/dma-map-ops.h&gt;</title>
<updated>2020-10-06T05:07:04Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-09-11T08:56:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0b1abd1fb7efafc25231c54a67c6fbb3d3127efd'/>
<id>urn:sha1:0b1abd1fb7efafc25231c54a67c6fbb3d3127efd</id>
<content type='text'>
Merge dma-contiguous.h into dma-map-ops.h, after removing the comment
describing the contiguous allocator into kernel/dma/contigous.c.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>dma-mapping: split &lt;linux/dma-mapping.h&gt;</title>
<updated>2020-10-06T05:07:03Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-09-22T13:31:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0a0f0d8be76dcd4390ff538e7060fda34db79717'/>
<id>urn:sha1:0a0f0d8be76dcd4390ff538e7060fda34db79717</id>
<content type='text'>
Split out all the bits that are purely for dma_map_ops implementations
and related code into a new &lt;linux/dma-map-ops.h&gt; header so that they
don't get pulled into all the drivers.  That also means the architecture
specific &lt;asm/dma-mapping.h&gt; is not pulled in by &lt;linux/dma-mapping.h&gt;
any more, which leads to a missing includes that were pulled in by the
x86 or arm versions in a few not overly portable drivers.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.</title>
<updated>2020-09-27T08:58:10Z</updated>
<author>
<name>周琰杰 (Zhou Yanjie)</name>
<email>zhouyanjie@wanyeetech.com</email>
</author>
<published>2020-09-22T01:24:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a5ce852398a4efc9df4869a71ff45b9dda58882d'/>
<id>urn:sha1:a5ce852398a4efc9df4869a71ff45b9dda58882d</id>
<content type='text'>
1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.

Signed-off-by: 周琰杰 (Zhou Yanjie) &lt;zhouyanjie@wanyeetech.com&gt;
Reviewed-by: Paul Cercueil &lt;paul@crapouillou.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>dma-mapping: remove dma_cache_sync</title>
<updated>2020-09-25T04:20:46Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-09-01T11:28:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5a84292271402cffe0717bc58e2ad9a0c7977272'/>
<id>urn:sha1:5a84292271402cffe0717bc58e2ad9a0c7977272</id>
<content type='text'>
All users are gone now, remove the API.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Acked-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt; (MIPS part)
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into dma-mapping-for-next</title>
<updated>2020-09-25T04:19:19Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-09-25T04:19:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8c1c6c7588b2faf9dd45fb3cfb7497fd09bbfe7c'/>
<id>urn:sha1:8c1c6c7588b2faf9dd45fb3cfb7497fd09bbfe7c</id>
<content type='text'>
Pull in the latest 5.9 tree for the commit to revert the
V4L2_FLAG_MEMORY_NON_CONSISTENT uapi addition.
</content>
</entry>
<entry>
<title>MIPS: make dma_sync_*_for_cpu a little less overzealous</title>
<updated>2020-09-11T06:13:49Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-08-18T13:18:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=cbf1449ba5aec9cf4c68b69f899391a8d42e9b8f'/>
<id>urn:sha1:cbf1449ba5aec9cf4c68b69f899391a8d42e9b8f</id>
<content type='text'>
When transferring DMA ownership back to the CPU there should never
be any writeback from the cache, as the buffer was owned by the
device until now.  Instead it should just be invalidated for the
mapping directions where the device could have written data.
Note that the changes rely on the fact that kmap_atomic is stubbed
out for the !HIGHMEM case to simplify the code a bit.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Acked-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR</title>
<updated>2020-09-07T20:25:16Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8e7291d603a3fa8f0d16feb825629c669f36c49e'/>
<id>urn:sha1:8e7291d603a3fa8f0d16feb825629c669f36c49e</id>
<content type='text'>
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX.
By using the version check we can remove the define.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Get rid of BCM1250_M3_WAR</title>
<updated>2020-09-07T20:25:03Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2020-08-24T16:32:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ab5743079b8e3d3d4309664903f6b1f579168a56'/>
<id>urn:sha1:ab5743079b8e3d3d4309664903f6b1f579168a56</id>
<content type='text'>
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
</feed>
