wireguard-linux/arch/ppc/kernel/misc.S, branch stable

powerpc: Remove arch/ppc and include/asm-ppc

2008-06-10T11:40:22Z

All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: Adrian Bunk Acked-by: Arnd Bergmann Acked-by: Becky Bruce Acked-by: Benjamin Herrenschmidt Acked-by: Geert Uytterhoeven Acked-by: Grant Likely Acked-by: Jochen Friedrich Acked-by: John Linn Acked-by: Jon Loeliger Acked-by: Josh Boyer Acked-by: Kumar Gala Acked-by: Olof Johansson Acked-by: Peter Korsgaard Acked-by: Scott Wood Acked-by: Sean MacLennan Acked-by: Segher Boessenkool Acked-by: Stefan Roese Acked-by: Stephen Neuendorffer Acked-by: Wolfgang Denk Signed-off-by: Paul Mackerras

[PPC] Remove 85xx from arch/ppc

2008-01-28T14:33:10Z

85xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala

[POWERPC] 4xx: Deal with 44x virtually tagged icache

2007-11-01T12:15:30Z

The 44x family has an interesting "feature" which is a virtually tagged instruction cache (yuck !). So far, we haven't dealt with it properly, which means we've been mostly lucky or people didn't report the problems, unless people have been running custom patches in their distro... This is an attempt at fixing it properly. I chose to do it by setting a global flag whenever we change a PTE that was previously marked executable, and flush the entire instruction cache upon return to user space when that happens. This is a bit heavy handed, but it's hard to do more fine grained flushes as the icbi instruction, on those processor, for some very strange reasons (since the cache is virtually mapped) still requires a valid TLB entry for reading in the target address space, which isn't something I want to deal with. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer

[POWERPC] 4xx: Fix 4xx flush_tlb_page()

2007-11-01T12:15:09Z

On 4xx CPUs, the current implementation of flush_tlb_page() uses a low level _tlbie() assembly function that only works for the current PID. Thus, invalidations caused by, for example, a COW fault triggered by get_user_pages() from a different context will not work properly, causing among other things, gdb breakpoints to fail. This patch adds a "pid" argument to _tlbie() on 4xx processors, and uses it to flush entries in the right context. FSL BookE also gets the argument but it seems they don't need it (their tlbivax form ignores the PID when invalidating according to the document I have). Signed-off-by: Benjamin Herrenschmidt Acked-by: Kumar Gala Signed-off-by: Josh Boyer

[POWERPC] Fix small race in 44x tlbie function

2007-08-15T05:12:50Z

The 440 family of processors don't have a tlbie instruction. So, we implement TLB invalidates by explicitly searching the TLB with tlbsx., then clobbering the relevant entry, if any. Unfortunately the PID for the search needs to be stored in the MMUCR register, which is also used by the TLB miss handler. Interrupts were enabled in _tlbie(), so an interrupt between loading the MMUCR and the tlbsx could cause incorrect search results, and thus a failure to invalide TLB entries which needed to be invalidated. This fixes the problem in both arch/ppc and arch/powerpc by inhibiting interrupts (even critical and debug interrupts) across the relevant instructions. Signed-off-by: David Gibson Acked-by: Josh Boyer Signed-off-by: Paul Mackerras

[POWERPC] Merge CPU features pertaining to icache coherency

2007-06-14T12:30:16Z

Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson Signed-off-by: Paul Mackerras

[POWERPC] Consolidate feature fixup code

2006-10-25T01:42:10Z

There are currently two versions of the functions for applying the feature fixups, one for CPU features and one for firmware features. In addition, they are both in assembly and with separate implementations for 32 and 64 bits. identify_cpu() is also implemented in assembly and separately for 32 and 64 bits. This patch replaces them with a pair of C functions. The call sites are slightly moved on ppc64 as well to be called from C instead of from assembly, though it's a very small change, and thus shouldn't cause any problem. Signed-off-by: Benjamin Herrenschmidt Acked-by: Olof Johansson Signed-off-by: Paul Mackerras

[PATCH] provide kernel_execve on all architectures

2006-10-02T14:57:23Z

This adds the new kernel_execve function on all architectures that were using _syscall3() to implement execve. The implementation uses code from the _syscall3 macros provided in the unistd.h header file. I don't have cross-compilers for any of these architectures, so the patch is untested with the exception of i386. Most architectures can probably implement this in a nicer way in assembly or by combining it with the sys_execve implementation itself, but this should do it for now. [bunk@stusta.de: m68knommu build fix] [markh@osdl.org: build fix] [bero@arklinux.org: build fix] [ralf@linux-mips.org: mips fix] [schwidefsky@de.ibm.com: s390 fix] Signed-off-by: Arnd Bergmann Cc: Andi Kleen Cc: Paul Mackerras Cc: Benjamin Herrenschmidt Cc: Richard Henderson Cc: Ivan Kokshaysky Cc: Russell King Cc: Ian Molton Cc: Mikael Starvik Cc: David Howells Cc: Yoshinori Sato Cc: Hirokazu Takata Cc: Ralf Baechle Cc: Kyle McMartin Cc: Heiko Carstens Cc: Martin Schwidefsky Cc: Paul Mundt Cc: Kazumoto Kojima Cc: Richard Curnow Cc: William Lee Irwin III Cc: "David S. Miller" Cc: Jeff Dike Cc: Paolo 'Blaisorblade' Giarrusso Cc: Miles Bader Cc: Chris Zankel Cc: "Luck, Tony" Cc: Geert Uytterhoeven Cc: Roman Zippel Signed-off-by: Ralf Baechle Signed-off-by: Bernhard Rosenkraenzer Signed-off-by: Mark Haverkamp Signed-off-by: Adrian Bunk Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[POWERPC] clean up ide io accessors

2006-09-20T04:06:18Z

Signed-off-by: Stephen Rothwell

[POWERPC] remove unused asm routines

2006-09-20T04:06:18Z

_insw, _outsw, _insl amd _outsl are all unused, so remove them. Signed-off-by: Stephen Rothwell