wireguard-linux/arch/ppc/kernel/setup.c, branch stable

powerpc: Remove arch/ppc and include/asm-ppc

2008-06-10T11:40:22Z

All the maintained platforms are now in arch/powerpc, so the old arch/ppc stuff can now go away. Acked-by: Adrian Bunk Acked-by: Arnd Bergmann Acked-by: Becky Bruce Acked-by: Benjamin Herrenschmidt Acked-by: Geert Uytterhoeven Acked-by: Grant Likely Acked-by: Jochen Friedrich Acked-by: John Linn Acked-by: Jon Loeliger Acked-by: Josh Boyer Acked-by: Kumar Gala Acked-by: Olof Johansson Acked-by: Peter Korsgaard Acked-by: Scott Wood Acked-by: Sean MacLennan Acked-by: Segher Boessenkool Acked-by: Stefan Roese Acked-by: Stephen Neuendorffer Acked-by: Wolfgang Denk Signed-off-by: Paul Mackerras

[POWERPC] ppc: More compile fixes

2008-05-12T12:57:51Z

This fixes a few more miscellaneous compile problems with ARCH=ppc. 1. Don't compile devres.c on ARCH=ppc, it doesn't have ioremap_flags. 2. Include in setup.c for the __DO_IRQ_CANON definition. 3. Include in residual.c for the definition of create_proc_read_entry. 4. Fix xchg_ptr to be a static inline to eliminate a compiler warning. Signed-off-by: Paul Mackerras

ppc: remove ppc_ide_md

2008-04-17T22:46:32Z

* Add special cases for pplus and prep to ide_default_{irq,io_base}() (+ FIXMEs about the need to use IDE platform host driver instead). * Remove no longer needed ppc_ide_md and struct ide_machdep_calls. * Then remove include from: - arch/powerpc/kernel/setup_32.c - arch/ppc/kernel/ppc_ksyms.c - arch/ppc/kernel/setup.c - arch/ppc/platforms/pplus.c - arch/ppc/platforms/prep_setup.c There should be no functional changes caused by this patch. Cc: Benjamin Herrenschmidt Signed-off-by: Bartlomiej Zolnierkiewicz

procfs: constify function pointer tables

2008-02-08T17:22:38Z

Signed-off-by: Jan Engelhardt Acked-by: Geert Uytterhoeven Acked-by: Mike Frysinger Acked-By: David Howells Acked-by: Bryan Wu Acked-by: Jesper Nilsson Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

[PPC] Remove 85xx from arch/ppc

2008-01-28T14:33:10Z

85xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala

[PPC] Remove 83xx from arch/ppc

2008-01-28T14:33:09Z

83xx exists in arch/powerpc as well as cuImage support to boot from a u-boot that doesn't support device trees. Signed-off-by: Kumar Gala

[POWERPC] arch/ppc: Remove duplicate includes

2007-12-20T06:13:50Z

Signed-off-by: Lucas Woods Cc: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras

[POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP

2007-11-19T14:22:20Z

This fixes arch/ppc 440EP platforms to setup the FPU correctly. A virtual PVR is used, as 440GR platforms share an identical hardware PVR value and do not have an FPU. Signed-off-by: Josh Boyer

[POWERPC] Remove APUS support from arch/ppc

2007-09-17T05:15:04Z

Current status of APUS: - arch/powerpc/: removed in 2.6.23 - arch/ppc/: marked BROKEN since 2 years This therefore removes the remaining parts of APUS support from arch/ppc, include/asm-ppc, arch/powerpc and include/asm-powerpc. Signed-off-by: Adrian Bunk Signed-off-by: Paul Mackerras

[POWERPC] Merge CPU features pertaining to icache coherency

2007-06-14T12:30:16Z

Currently the powerpc kernel has a 64-bit only feature, COHERENT_ICACHE used for those CPUS which maintain icache/dcache coherency in hardware (POWER5, essentially). It also has a feature, SPLIT_ID_CACHE, which is used on CPUs which have separate i and d-caches, which is to say everything except 601 and Freescale E200. In nearly all the places we check the SPLIT_ID_CACHE, what we actually care about is whether the i and d-caches are coherent (which they will be, trivially, if they're the same cache). This tries to clarify the situation a little. The COHERENT_ICACHE feature becomes availble on 32-bit and is set for all CPUs where i and d-cache are effectively coherent, whether this is due to special logic (POWER5) or because they're unified. We check this, instead of SPLIT_ID_CACHE nearly everywhere. The SPLIT_ID_CACHE feature itself is replaced by a UNIFIED_ID_CACHE feature with reversed sense, set only on 601 and Freescale E200. In the two places (one Freescale BookE specific) where we really care whether it's a unified cache, not whether they're coherent, we check this feature. The CPUs with unified cache are so few, we could consider replacing this feature bit with explicit checks against the PVR. This will make unifying the 32-bit and 64-bit cache flush code a little more straightforward. Signed-off-by: David Gibson Signed-off-by: Paul Mackerras