<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/riscv/Makefile, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/riscv/Makefile?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/riscv/Makefile?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-08-08T01:24:32Z</updated>
<entry>
<title>riscv: cmpxchg: Use .option arch for Zacas and Zabha</title>
<updated>2026-08-08T01:24:32Z</updated>
<author>
<name>Vivian Wang</name>
<email>wangruikang@iscas.ac.cn</email>
</author>
<published>2026-08-08T01:24:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=76555252981eefa209ba2a16544c4f1704ca330b'/>
<id>urn:sha1:76555252981eefa209ba2a16544c4f1704ca330b</id>
<content type='text'>
Instead of adding these to -march globally, use .option arch to use
instructions from these extensions only in code paths where we know they
are available, like how it is done for most other extensions.
TOOLCHAIN_HAS_{ZACAS,ZABHA} already depend on AS_HAS_OPTION_ARCH, so
this is not a functionality regression even on older assemblers.

Although the compiler is unlikely to generate atomics on its own accord,
this aligns handling of Zacas and Zabha with most other extensions and
improves consistency on how assembly code requiring extra extensions is
written in kernel code.

This is analogous to the use of __LSE_PREAMBLE or .arch_extension lse in
arm64 code.

Signed-off-by: Vivian Wang &lt;wangruikang@iscas.ac.cn&gt;
Reviewed-by: Jesse Taube &lt;jtaubepe@redhat.com&gt;
Link: https://patch.msgid.link/20260717-riscv-no-zacas-zabha-in-march-v1-1-82b5b0799fb6@iscas.ac.cn
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: further remove XIP</title>
<updated>2026-08-08T01:24:32Z</updated>
<author>
<name>Jisheng Zhang</name>
<email>jszhang@kernel.org</email>
</author>
<published>2026-08-08T01:24:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=abcdefbe49655c1b8b12445f73e6116b4f123db2'/>
<id>urn:sha1:abcdefbe49655c1b8b12445f73e6116b4f123db2</id>
<content type='text'>
After commit 9b3a2be84803 ("riscv: Remove support for XIP kernel"),
something relatd with XIP are still there. Remove them to clean up the
code.

Signed-off-by: Jisheng Zhang &lt;jszhang@kernel.org&gt;
Reviewed-by: Nam Cao &lt;namcao@linutronix.de&gt;
Link: https://patch.msgid.link/20260805010049.13918-1-jszhang@kernel.org
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: vdso: Only try to install vDSO when present</title>
<updated>2026-07-29T23:55:17Z</updated>
<author>
<name>Thomas Weißschuh</name>
<email>thomas.weissschuh@linutronix.de</email>
</author>
<published>2026-07-09T06:49:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c052927905710de1ab7364bf1925efbd12517ea3'/>
<id>urn:sha1:c052927905710de1ab7364bf1925efbd12517ea3</id>
<content type='text'>
vdso.so.dbg is only built with CONFIG_MMU.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202607090258.iSAUYlO1-lkp@intel.com/
Fixes: f157d411a9eb ("riscv: add missing vdso_install target")
Fixes: 3edf39916977 ("vDSO, kbuild: Provide vDSO debug variants at runtime")
Signed-off-by: Thomas Weißschuh &lt;thomas.weissschuh@linutronix.de&gt;
Link: https://patch.msgid.link/20260709-riscv-install-vdso-v1-1-0ba4345419ca@linutronix.de
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: Remove support for XIP kernel</title>
<updated>2026-04-05T00:42:44Z</updated>
<author>
<name>Nam Cao</name>
<email>namcao@linutronix.de</email>
</author>
<published>2026-04-04T01:28:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9b3a2be84803cf18c4b4d1efc695991f0daa153c'/>
<id>urn:sha1:9b3a2be84803cf18c4b4d1efc695991f0daa153c</id>
<content type='text'>
XIP has a history of being broken for long periods of time. In 2023, it was
broken for 18 months before getting fixed [1]. In 2024 it was 4 months [2].

And now it is broken again since commit a44fb5722199 ("riscv: Add runtime
constant support"), 10 months ago.

These are clear signs that XIP feature is not being used.

I occasionally looked after XIP, but mostly because I was bored and had
nothing better to do.

Remove XIP support. Revert is possible if someone shows up complaining.

Link: https://lore.kernel.org/linux-riscv/20231212-customary-hardcover-e19462bf8e75@wendy/ [1]
Link: https://lore.kernel.org/linux-riscv/20240526110104.470429-1-namcao@linutronix.de/ [2]
Signed-off-by: Nam Cao &lt;namcao@linutronix.de&gt;
Cc: Frederik Haxel &lt;haxel@fzi.de&gt;
Cc: Vitaly Wool &lt;vitaly.wool@konsulko.com&gt;
Reviewed-by: Jisheng Zhang &lt;jszhang@kernel.org&gt;
Acked-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Link: https://patch.msgid.link/20260202115403.2119218-1-namcao@linutronix.de
[pjw@kernel.org: updated to apply]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: Simplify assignment for UTS_MACHINE</title>
<updated>2026-04-05T00:42:40Z</updated>
<author>
<name>Uwe Kleine-König</name>
<email>u.kleine-koenig@baylibre.com</email>
</author>
<published>2026-04-05T00:42:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c8d0c36d852ccd7caf9d5a44f3090f80a060c28d'/>
<id>urn:sha1:c8d0c36d852ccd7caf9d5a44f3090f80a060c28d</id>
<content type='text'>
The BITS variable conveniently allows to simplify the assignment for
UTS_MACHINE.

Signed-off-by: Uwe Kleine-König (The Capable Hub) &lt;u.kleine-koenig@baylibre.com&gt;
Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>arch/riscv: add dual vdso creation logic and select vdso based on hw</title>
<updated>2026-01-29T09:38:40Z</updated>
<author>
<name>Deepak Gupta</name>
<email>debug@rivosinc.com</email>
</author>
<published>2026-01-26T04:09:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ccad8c1336b6511e3c7ca5c02f797b1fd2cf67e1'/>
<id>urn:sha1:ccad8c1336b6511e3c7ca5c02f797b1fd2cf67e1</id>
<content type='text'>
Shadow stack instructions are taken from the Zimop ISA extension,
which is mandated on RVA23. Any userspace with shadow stack
instructions in it will fault on hardware that doesn't have support
for Zimop.  Thus, a shadow stack-enabled userspace can't be run on
hardware that doesn't support Zimop.

It's not known how Linux userspace providers will respond to this kind
of binary fragmentation.  In order to keep kernel portable across
different hardware, 'arch/riscv/kernel/vdso_cfi' is created which has
Makefile logic to compile 'arch/riscv/kernel/vdso' sources with CFI
flags, and 'arch/riscv/kernel/vdso.c' is modified to select the
appropriate vdso depending on whether the underlying CPU implements
the Zimop extension. Since the offset of vdso symbols will change due
to having two different vdso binaries, there is added logic to include
a new generated vdso offset header and dynamically select the offset
(like for rt_sigreturn).

Signed-off-by: Deepak Gupta &lt;debug@rivosinc.com&gt;
Acked-by: Charles Mirabile &lt;cmirabil@redhat.com&gt;
Tested-by: Andreas Korb &lt;andreas.korb@aisec.fraunhofer.de&gt; # QEMU, custom CVA6
Tested-by: Valentin Haudiquet &lt;valentin.haudiquet@canonical.com&gt;
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-24-b55691eacf4f@rivosinc.com
[pjw@kernel.org: cleaned up patch description]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>arch/riscv: compile vdso with landing pad and shadow stack note</title>
<updated>2026-01-29T09:38:40Z</updated>
<author>
<name>Jim Shu</name>
<email>jim.shu@sifive.com</email>
</author>
<published>2026-01-26T04:09:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=37f57bd3faeac92e898c3381355f4fd2b6a80901'/>
<id>urn:sha1:37f57bd3faeac92e898c3381355f4fd2b6a80901</id>
<content type='text'>
User mode tasks compiled with Zicfilp may call indirectly into the
vdso (like hwprobe indirect calls). Add support for compiling landing
pads into the vdso. Landing pad instructions in the vdso will be
no-ops for tasks which have not enabled landing pads. Furthermore, add
support for the C sources of the vdso to be compiled with shadow stack
and landing pads enabled as well.

Landing pad and shadow stack instructions are emitted only when the
VDSO_CFI cflags option is defined during compile.

Signed-off-by: Jim Shu &lt;jim.shu@sifive.com&gt;
Reviewed-by: Zong Li &lt;zong.li@sifive.com&gt;
Signed-off-by: Deepak Gupta &lt;debug@rivosinc.com&gt;
Tested-by: Andreas Korb &lt;andreas.korb@aisec.fraunhofer.de&gt; # QEMU, custom CVA6
Tested-by: Valentin Haudiquet &lt;valentin.haudiquet@canonical.com&gt;
Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-23-b55691eacf4f@rivosinc.com
[pjw@kernel.org: cleaned up patch description, issues reported by checkpatch]
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;
</content>
</entry>
<entry>
<title>riscv: Remove redundant judgment for the default build target</title>
<updated>2025-11-08T00:39:07Z</updated>
<author>
<name>Feng Jiang</name>
<email>jiangfeng@kylinos.cn</email>
</author>
<published>2025-10-29T09:44:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5e8632987dd1882ed4d1e1039032ab1b0c1ec12b'/>
<id>urn:sha1:5e8632987dd1882ed4d1e1039032ab1b0c1ec12b</id>
<content type='text'>
The value of KBUILD_IMAGE is derived from $(boot-image-y),
so there's no need for redundant checks before this.

Signed-off-by: Feng Jiang &lt;jiangfeng@kylinos.cn&gt;
Reviewed-by: Emil Renner Berthing &lt;emil.renner.berthing@canonical.com&gt;
Link: https://lore.kernel.org/r/20251029094429.553842-2-jiangfeng@kylinos.cn
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: Build loader.bin exclusively for Canaan K210</title>
<updated>2025-11-08T00:39:06Z</updated>
<author>
<name>Feng Jiang</name>
<email>jiangfeng@kylinos.cn</email>
</author>
<published>2025-10-29T09:44:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3ad1b71fdc5707d14332d9ae710a237de936be9b'/>
<id>urn:sha1:3ad1b71fdc5707d14332d9ae710a237de936be9b</id>
<content type='text'>
According to the explanation in commit ef10bdf9c3e6 ("riscv:
Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210"),
loader.bin is a special feature of the Canaan K210 and
is not applicable to other SoCs.

Fixes: e79dfcbfb902 ("riscv: make image compression configurable")
Signed-off-by: Feng Jiang &lt;jiangfeng@kylinos.cn&gt;
Reviewed-by: Emil Renner Berthing &lt;emil.renner.berthing@canonical.com&gt;
Link: https://lore.kernel.org/r/20251029094429.553842-1-jiangfeng@kylinos.cn
Signed-off-by: Paul Walmsley &lt;pjw@kernel.org&gt;</content>
</entry>
<entry>
<title>riscv: Unconditionally use linker relaxation</title>
<updated>2025-08-28T23:58:45Z</updated>
<author>
<name>Nathan Chancellor</name>
<email>nathan@kernel.org</email>
</author>
<published>2025-08-21T21:15:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7ccbe91796d7bb584a00833cb59ef7d4575ba784'/>
<id>urn:sha1:7ccbe91796d7bb584a00833cb59ef7d4575ba784</id>
<content type='text'>
Now that the minimum supported version of LLVM for building the kernel
has been bumped to 15.0.0, CONFIG_RISCV_USE_LINKER_RELAXATION will
always be enabled, so it can be removed.

Acked-by: Alexandre Ghiti &lt;alexghiti@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20250821-bump-min-llvm-ver-15-v2-8-635f3294e5f0@kernel.org
Signed-off-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
</content>
</entry>
</feed>
