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<title>wireguard-linux/arch/riscv/boot, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/riscv/boot?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/riscv/boot?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-09T17:51:30Z</updated>
<entry>
<title>Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux</title>
<updated>2020-04-09T17:51:30Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-04-09T17:51:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=eab40026605f4717a9749ffcaec8119d58494999'/>
<id>urn:sha1:eab40026605f4717a9749ffcaec8119d58494999</id>
<content type='text'>
Pull RISC-V updates from Palmer Dabbelt:
 "This contains a handful of new features:

   - Partial support for the Kendryte K210.

     There are still a few outstanding issues that I have patches for,
     but I don't actually have a board to test them so they're not
     included yet.

   - SBI v0.2 support.

   - Fixes to support for building with LLVM-based toolchains. The
     resulting images are known not to boot yet.

  I don't anticipate a part two, but I'll probably have something early
  in the RCs to finish up the K210 support"

* tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits)
  riscv: create a loader.bin boot image for Kendryte SoC
  riscv: Kendryte K210 default config
  riscv: Add Kendryte K210 device tree
  riscv: Select required drivers for Kendryte SOC
  riscv: Add Kendryte K210 SoC support
  riscv: Add SOC early init support
  riscv: Unaligned load/store handling for M_MODE
  RISC-V: Support cpu hotplug
  RISC-V: Add supported for ordered booting method using HSM
  RISC-V: Add SBI HSM extension definitions
  RISC-V: Export SBI error to linux error mapping function
  RISC-V: Add cpu_ops and modify default booting method
  RISC-V: Move relocate and few other functions out of __init
  RISC-V: Implement new SBI v0.2 extensions
  RISC-V: Introduce a new config for SBI v0.1
  RISC-V: Add SBI v0.2 extension definitions
  RISC-V: Add basic support for SBI v0.2
  RISC-V: Mark existing SBI as 0.1 SBI.
  riscv: Use macro definition instead of magic number
  riscv: Add support to dump the kernel page tables
  ...
</content>
</entry>
<entry>
<title>riscv: create a loader.bin boot image for Kendryte SoC</title>
<updated>2020-04-03T17:50:17Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-03-16T00:47:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=37809df4b1c88927fe944eb766e0553811c51f64'/>
<id>urn:sha1:37809df4b1c88927fe944eb766e0553811c51f64</id>
<content type='text'>
Create the loader.bin bootable image file that can be loaded into
Kendryte K210 based boards using the kflash.py tool with the command:

kflash.py/kflash.py -t arch/riscv/boot/loader.bin

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Damien Le Moal &lt;damien.lemoal@wdc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Reviewed-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: Add Kendryte K210 device tree</title>
<updated>2020-04-03T17:50:15Z</updated>
<author>
<name>Damien Le Moal</name>
<email>damien.lemoal@wdc.com</email>
</author>
<published>2020-03-16T00:47:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5ba568f57f0ae4826beb6aaeecb12e68219b8a0b'/>
<id>urn:sha1:5ba568f57f0ae4826beb6aaeecb12e68219b8a0b</id>
<content type='text'>
Add a generic device tree for Kendryte K210 SoC based boards. This is
for now a very simple device tree describing the core elements of the
SoC. This is suitable (and tested) for the Kendryte KD233 development
board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.

Signed-off-by: Damien Le Moal &lt;damien.lemoal@wdc.com&gt;
Reviewed-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>.gitignore: add SPDX License Identifier</title>
<updated>2020-03-25T10:50:48Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>masahiroy@kernel.org</email>
</author>
<published>2020-03-03T13:35:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d198b34f3855eee2571dda03eea75a09c7c31480'/>
<id>urn:sha1:d198b34f3855eee2571dda03eea75a09c7c31480</id>
<content type='text'>
Add SPDX License Identifier to all .gitignore files.

Signed-off-by: Masahiro Yamada &lt;masahiroy@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file</title>
<updated>2020-03-05T20:27:10Z</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2020-02-19T03:49:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0a91330b2af9f71ceeeed483f92774182b58f6d9'/>
<id>urn:sha1:0a91330b2af9f71ceeeed483f92774182b58f6d9</id>
<content type='text'>
Add the ability to reboot the HiFive Unleashed board via GPIO.

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: Fix gitignore</title>
<updated>2020-02-20T00:13:51Z</updated>
<author>
<name>Damien Le Moal</name>
<email>damien.lemoal@wdc.com</email>
</author>
<published>2020-02-12T10:34:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e7167043ee508739fc9c5030494f94bea48cee23'/>
<id>urn:sha1:e7167043ee508739fc9c5030494f94bea48cee23</id>
<content type='text'>
Tell git to not track the compiled boot/loader and boot/loader.lds
files.

Signed-off-by: Damien Le Moal &lt;damien.lemoal@wdc.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: dts: Add DT support for SiFive FU540 GPIO driver</title>
<updated>2020-01-29T14:58:08Z</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2019-12-10T11:11:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=61ffb9d27860769c5d5596f6e4cca3cded2755e0'/>
<id>urn:sha1:61ffb9d27860769c5d5596f6e4cca3cded2755e0</id>
<content type='text'>
Add the gpio DT node in SiFive FU540 soc-specific DT file.
Enable the gpio node in HiFive Unleashed board-specific DT file.

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: dts: Add DT support for SiFive L2 cache controller</title>
<updated>2020-01-03T08:56:23Z</updated>
<author>
<name>Yash Shah</name>
<email>yash.shah@sifive.com</email>
</author>
<published>2020-01-03T04:13:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=cfda8617e22a8bf217a613d0b3ba3a38778443ba'/>
<id>urn:sha1:cfda8617e22a8bf217a613d0b3ba3a38778443ba</id>
<content type='text'>
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file

Signed-off-by: Yash Shah &lt;yash.shah@sifive.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>riscv: Fix build dependency for loader</title>
<updated>2019-12-09T04:19:30Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2019-12-07T21:29:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0e72a2f9c1a386aaa8337f9f524f89a7884b82cf'/>
<id>urn:sha1:0e72a2f9c1a386aaa8337f9f524f89a7884b82cf</id>
<content type='text'>
The Makefile addition for the flat image loader missed an obj prefix.

For most parallel builds this worked out fine, but with -j1 the dependency
wasn't fulfilled and thus fails:

arch/riscv/boot/loader.S: Assembler messages:
arch/riscv/boot/loader.S:7: Error: file not found: arch/riscv/boot/Image

Fixes: 405fe7aa0dba ("riscv: provide a flat image loader")
Cc: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>Merge branch 'next/nommu' into for-next</title>
<updated>2019-11-23T02:59:09Z</updated>
<author>
<name>Paul Walmsley</name>
<email>paul.walmsley@sifive.com</email>
</author>
<published>2019-11-23T02:59:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5ba9aa56e6d3e8fddb954c2f818d1ce0525235bb'/>
<id>urn:sha1:5ba9aa56e6d3e8fddb954c2f818d1ce0525235bb</id>
<content type='text'>
Conflicts:
	arch/riscv/boot/Makefile
	arch/riscv/include/asm/sbi.h
</content>
</entry>
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