wireguard-linux/arch/riscv/include/asm/set_memory.h, branch jd/unified-crypt-queue

riscv: add STRICT_KERNEL_RWX support

2020-03-26T16:24:45Z

The commit contains that make text section as non-writable, rodata section as read-only, and data section as non-executable. The init section should be changed to non-executable. Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt

riscv: add alignment for text, rodata and data sections

2020-03-26T16:24:42Z

The kernel mapping will tried to optimize its mapping by using bigger size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in rv32. To ensure that the start address of these sections could fit the mapping entry size, make them align to the biggest alignment. Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc., are invisible in linker script. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt

riscv: add ARCH_HAS_SET_DIRECT_MAP support

2020-03-26T16:24:33Z

Add set_direct_map_*() functions for setting the direct map alias for the page to its default permissions and to an invalid state that cannot be cached in a TLB. (See d253ca0c ("x86/mm/cpa: Add set_direct_map_*() functions")) Add a similar implementation for RISC-V. Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt

riscv: add ARCH_HAS_SET_MEMORY support

2020-03-26T16:24:30Z

Add set_memory_ro/rw/x/nx architecture hooks to change the page attribution. Use own set_memory.h rather than generic set_memory.h (i.e. include/asm-generic/set_memory.h), because we want to add other function prototypes here. Signed-off-by: Zong Li Signed-off-by: Palmer Dabbelt