<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/s390/kernel/entry.S, branch update-toolchain</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/s390/kernel/entry.S?h=update-toolchain</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/s390/kernel/entry.S?h=update-toolchain'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-07-23T14:02:32Z</updated>
<entry>
<title>s390/entry: Make system_call() ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=361f6ec2fe203760353c708480099e0325295b21'/>
<id>urn:sha1:361f6ec2fe203760353c708480099e0325295b21</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in system_call().

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Make ret_from_fork() ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9b3dcae128f8803950d646329f2301cae3fe8f4d'/>
<id>urn:sha1:9b3dcae128f8803950d646329f2301cae3fe8f4d</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in ret_from_fork().

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Make __switch_to() ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7cc86dee44a47d961fd6195fd91f75ce176b992d'/>
<id>urn:sha1:7cc86dee44a47d961fd6195fd91f75ce176b992d</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in __switch_to().

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Make restart_int_handler() ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4064b711127e1eb5b5fd42d539fd45e3e33c9b6f'/>
<id>urn:sha1:4064b711127e1eb5b5fd42d539fd45e3e33c9b6f</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in restart_int_handler().

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Make mchk_int_handler() ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0001b7bbc53aeb8d31f650701d2a55e498634a2d'/>
<id>urn:sha1:0001b7bbc53aeb8d31f650701d2a55e498634a2d</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in mcck_int_handler().

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Make int handlers ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=bd2c55b307f77fbf19d76250672266ff06f4a324'/>
<id>urn:sha1:bd2c55b307f77fbf19d76250672266ff06f4a324</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in the ext/io interrupt
handlers.

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Make pgm_check_handler() ready for lowcore relocation</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9e1e275fa28d5896ca7cdf8afa5eb58c0117a303'/>
<id>urn:sha1:9e1e275fa28d5896ca7cdf8afa5eb58c0117a303</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to all lowcore accesses in pgm_check_handler().

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Add base register to CHECK_VMAP_STACK/CHECK_STACK macro</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=86e08d64eec35cbe6a85798add4bfc1218ca9513'/>
<id>urn:sha1:86e08d64eec35cbe6a85798add4bfc1218ca9513</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to CHECK_VMAP_STACK and CHECK_STACK. No
functional change, because %r0 is passed to the macro.

Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Add base register to SIEEXIT macro</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6908f8f916f24636621a5b4c300bdf9a0155f07e'/>
<id>urn:sha1:6908f8f916f24636621a5b4c300bdf9a0155f07e</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to SIEEXIT. No functional change, because
%r0 is passed to the macro.

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
<entry>
<title>s390/entry: Add base register to MBEAR macro</title>
<updated>2024-07-23T14:02:32Z</updated>
<author>
<name>Sven Schnelle</name>
<email>svens@linux.ibm.com</email>
</author>
<published>2024-07-22T13:41:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ca2f0a26c498c42fcccdf09527e8755481801eea'/>
<id>urn:sha1:ca2f0a26c498c42fcccdf09527e8755481801eea</id>
<content type='text'>
In preparation of having lowcore at different address than zero,
add the base register to MBEAR. No functional change, because
%r0 is passed to the macro.

Reviewed-by: Heiko Carstens &lt;hca@linux.ibm.com&gt;
Signed-off-by: Sven Schnelle &lt;svens@linux.ibm.com&gt;
Signed-off-by: Vasily Gorbik &lt;gor@linux.ibm.com&gt;
</content>
</entry>
</feed>
