<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/xtensa/include/asm/cmpxchg.h, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/xtensa/include/asm/cmpxchg.h?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/xtensa/include/asm/cmpxchg.h?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2019-11-26T19:33:39Z</updated>
<entry>
<title>xtensa: use "m" constraint instead of "a" in cmpxchg.h assembly</title>
<updated>2019-11-26T19:33:39Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-10-16T07:49:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=cf3b3baa712517c4972339b150f79fa88099e5db'/>
<id>urn:sha1:cf3b3baa712517c4972339b150f79fa88099e5db</id>
<content type='text'>
Use "m" constraint instead of "r" for the address, as "m" allows
compiler to access adjacent locations using base + offset, while "r"
requires updating the base register every time.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: use named assembly arguments in cmpxchg.h</title>
<updated>2019-11-26T19:33:39Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-10-16T08:52:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=812e708a4c2d29664a009805671d98cbe7c756b1'/>
<id>urn:sha1:812e708a4c2d29664a009805671d98cbe7c756b1</id>
<content type='text'>
Numeric assembly arguments are hard to understand and assembly code that
uses them is hard to modify. Use named arguments in __cmpxchg_u32 and
xchg_u32.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: add exclusive atomics support</title>
<updated>2019-05-07T17:36:31Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-12-21T01:18:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f7c34874f04a80d6c39a32f08da2529e59602d3c'/>
<id>urn:sha1:f7c34874f04a80d6c39a32f08da2529e59602d3c</id>
<content type='text'>
Implement atomic primitives using exclusive access opcodes available in
the recent xtensa cores.
Since l32ex/s32ex don't have any memory ordering guarantees don't define
__smp_mb__before_atomic/__smp_mb__after_atomic to make them use memw.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: provide xchg for sizes 1 and 2</title>
<updated>2019-02-07T20:24:17Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-01-02T03:29:07Z</published>
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<id>urn:sha1:af3d890b4303cfc9df4b785c852246d4c7013436</id>
<content type='text'>
This is required for generic queued spinlocks, implement it.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: implement fake NMI</title>
<updated>2015-08-17T04:33:39Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-07-16T07:37:31Z</published>
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<id>urn:sha1:38fef73c21d117cf992fb5ec6e30630e54e13f4f</id>
<content type='text'>
In case perf IRQ is the highest of the medium-level IRQs, and is alone
on its level, it may be treated as NMI:
- LOCKLEVEL is defined to be one level less than EXCM level,
- IRQ masking never lowers current IRQ level,
- new fake exception cause code, EXCCAUSE_MAPPED_NMI is assigned to that
  IRQ; new second level exception handler, do_nmi, assigned to it
  handles it as NMI,
- atomic operations in configurations without s32c1i still need to mask
  all interrupts.

Cc: Peter Zijlstra &lt;a.p.zijlstra@chello.nl&gt;
Acked-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>arch: xtensa: include: asm: compiling issue, need cmpxchg64() defined.</title>
<updated>2013-06-05T17:14:21Z</updated>
<author>
<name>Chen Gang</name>
<email>gang.chen@asianux.com</email>
</author>
<published>2013-05-27T11:57:01Z</published>
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<id>urn:sha1:b5514786ec3257c8703fc7f29bdf98b42253ee39</id>
<content type='text'>
When compiling with 'allmodconfig', some of drivers need cmpxchg64(),
xtensa does not supply 64-bit implementation for 'xchg', so use the
'generic' implementation.

e.g. (for next-20130527 tree):
  drivers/block/blockconsole.c:164:2: error: implicit declaration of function ‘cmpxchg64’ [-Werror=implicit-function-declaration]

Signed-off-by: Chen Gang &lt;gang.chen@asianux.com&gt;
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
<entry>
<title>xtensa: clean up files to make them code-style compliant</title>
<updated>2012-12-19T05:10:25Z</updated>
<author>
<name>Chris Zankel</name>
<email>chris@zankel.net</email>
</author>
<published>2012-11-29T00:53:51Z</published>
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<id>urn:sha1:c4c4594b005d89b56964071bbbdeb07daac5bc76</id>
<content type='text'>
Remove heading and trailing spaces, trim trailing lines, and wrap lines
that are longer than 80 characters.

Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
<entry>
<title>xtensa: add s32c1i-based atomic ops implementations</title>
<updated>2012-12-19T05:10:22Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2012-11-10T23:30:02Z</published>
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<id>urn:sha1:219b1e4c61c108731bb665962231b1fa057f6c71</id>
<content type='text'>
Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
<entry>
<title>xtensa: reorganize SR referencing</title>
<updated>2012-10-16T04:48:08Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2012-10-14T23:55:38Z</published>
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<id>urn:sha1:bc5378fcba974317f9657c4fdc78af227e1e1068</id>
<content type='text'>
- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
Signed-off-by: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
<entry>
<title>Disintegrate asm/system.h for Xtensa</title>
<updated>2012-03-28T17:30:03Z</updated>
<author>
<name>David Howells</name>
<email>dhowells@redhat.com</email>
</author>
<published>2012-03-28T17:30:03Z</published>
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<id>urn:sha1:f9aa7e1882f3ceec919b30f64a2ce6e66a2571b1</id>
<content type='text'>
Disintegrate asm/system.h for Xtensa.

Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
cc: Chris Zankel &lt;chris@zankel.net&gt;
</content>
</entry>
</feed>
