<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/arch/xtensa/include/asm/initialize_mmu.h, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/arch/xtensa/include/asm/initialize_mmu.h?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/arch/xtensa/include/asm/initialize_mmu.h?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2019-10-21T06:48:29Z</updated>
<entry>
<title>xtensa: move MPU constants from .data to .ref.rodata</title>
<updated>2019-10-21T06:48:29Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-09-30T02:55:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6af4ab570db3dc71e877271a17e5e2b337e0bdc0'/>
<id>urn:sha1:6af4ab570db3dc71e877271a17e5e2b337e0bdc0</id>
<content type='text'>
MPU attribute mapping table is R/O, move it from .data to __REFCONST
(as the rest of the _startup code where initialize_cacheattr is used is
in the __REF section). This allows executing initialize_cacheattr before
the data section of the XIP kernel is relocated to its place.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>docs: xtensa: convert to ReST</title>
<updated>2019-07-15T12:20:26Z</updated>
<author>
<name>Mauro Carvalho Chehab</name>
<email>mchehab+samsung@kernel.org</email>
</author>
<published>2019-04-18T17:34:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8ea0afa3b801e9fe3ff676c3e60e74afa1a0848a'/>
<id>urn:sha1:8ea0afa3b801e9fe3ff676c3e60e74afa1a0848a</id>
<content type='text'>
Rename the xtensa documentation files to ReST, add an
index for them and adjust in order to produce a nice html
output via the Sphinx build system.

At its new index.rst, let's add a :orphan: while this is not linked to
the main index.rst file, in order to avoid build warnings.

Signed-off-by: Mauro Carvalho Chehab &lt;mchehab+samsung@kernel.org&gt;
</content>
</entry>
<entry>
<title>xtensa: implement initialize_cacheattr for MPU cores</title>
<updated>2019-05-07T17:36:34Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-05-06T23:47:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a5944195d00a359e28d6e093593609bcee37ed5e'/>
<id>urn:sha1:a5944195d00a359e28d6e093593609bcee37ed5e</id>
<content type='text'>
Use CONFIG_MEMMAP_CACHEATTR to initialize MPU as described in the Xtensa
LSP RM document. Coalesce adjacent regions with the same cacheattr.
Update Kconfig help text.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: replace variant/core.h with asm/core.h</title>
<updated>2019-05-07T00:48:55Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2019-01-02T03:41:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8f8d5745bb520c76b81abef4a2cb3023d0313bfd'/>
<id>urn:sha1:8f8d5745bb520c76b81abef4a2cb3023d0313bfd</id>
<content type='text'>
Introduce the header arch/xtensa/include/asm/core.h that provides
definitions for XCHAL macros missing in older xtensa releases. Use this
header instead of variant/core.h

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: rework noMMU cache attributes initialization</title>
<updated>2018-08-14T03:08:19Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2018-08-12T13:01:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7bb516ca5424e12b42124fab2906b6da9c81ba9c'/>
<id>urn:sha1:7bb516ca5424e12b42124fab2906b6da9c81ba9c</id>
<content type='text'>
Marking default memory region as cached is not always sufficient and is
not flexible. Allow specifying cache attributes for the whole memory
address space with new config entry MEMMAP_CACHEATTR. Apply it after
cache initialization.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: cleanup MMU setup and kernel layout macros</title>
<updated>2016-07-24T03:33:58Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-04-13T02:20:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a9f2fc628e3a26a829fd79aff74eb49839d1e74b'/>
<id>urn:sha1:a9f2fc628e3a26a829fd79aff74eb49839d1e74b</id>
<content type='text'>
Make kernel load address explicit, independent of the selected MMU
configuration and configurable from Kconfig. Do not restrict it to the
first 512MB of the physical address space.

Cleanup kernel memory layout macros:

- rename VECBASE_RESET_VADDR to VECBASE_VADDR, XC_VADDR to VECTOR_VADDR;
- drop VIRTUAL_MEMORY_ADDRESS and LOAD_MEMORY_ADDRESS;
- introduce PHYS_OFFSET and use it in __va and __pa definitions;
- synchronize MMU/noMMU vectors, drop unused NMI vector;
- replace hardcoded vectors offset of 0x3000 with Kconfig symbol.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: add alternative kernel memory layouts</title>
<updated>2016-07-24T03:33:58Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2016-04-11T18:14:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d39af90265feb40ec198c4ca8268724645b4b50e'/>
<id>urn:sha1:d39af90265feb40ec198c4ca8268724645b4b50e</id>
<content type='text'>
MMUv3 is able to support low memory bigger than 128MB.
Implement 256MB and 512MB KSEG layouts:

- add Kconfig selector for KSEG layout;
- add KSEG base address, size and alignment definitions to
  arch/xtensa/include/asm/kmem_layout.h;
- use new definitions in TLB initialization;
- add build time memory map consistency checks.

See Documentation/xtensa/mmu.txt for the details of new memory layouts.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: fix build for configs without cache options</title>
<updated>2015-11-02T15:02:51Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2015-09-24T20:20:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=01618bded680573163403666d0546be536b22ac0'/>
<id>urn:sha1:01618bded680573163403666d0546be536b22ac0</id>
<content type='text'>
- make cache-related assembly macros empty if core doesn't have
  corresponding cache type;
- don't initialize cache attributes in instruction/data TLB entries if
  there's no corresponding cache type.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: nommu: set up cache and atomctl in initialize_mmu</title>
<updated>2014-10-21T09:28:56Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2014-10-04T14:50:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2eabc1800d1ef7a850672aedcc266a831572af63'/>
<id>urn:sha1:2eabc1800d1ef7a850672aedcc266a831572af63</id>
<content type='text'>
initialize_mmu sets up atomctl SR which is needed for s32c1i to function
correctly even in noMMU configurations. It's also a good place to set up
caching attributes of physical memory.

Allow enabling INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX in noMMU
configurations for setting up atomctl and cache attributes.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
<entry>
<title>xtensa: move vecbase SR initialization to _startup</title>
<updated>2014-10-21T09:28:55Z</updated>
<author>
<name>Max Filippov</name>
<email>jcmvbkbc@gmail.com</email>
</author>
<published>2014-10-04T01:12:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=53490121e9ffa3e6314137af016cde8ac83c9bb4'/>
<id>urn:sha1:53490121e9ffa3e6314137af016cde8ac83c9bb4</id>
<content type='text'>
Instead of initializing vecbase in initialize_mmu macro, which may be
expanded either in Image.elf reset vector hadler or in the kernel
head.S, both times only when CONFIG_MMU is enabled, do this
initialization once in _startup function.

Signed-off-by: Max Filippov &lt;jcmvbkbc@gmail.com&gt;
</content>
</entry>
</feed>
