<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/clk/imx, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/clk/imx?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/clk/imx?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-10-20T16:29:23Z</updated>
<entry>
<title>clk: imx8mq: Fix usdhc parents order</title>
<updated>2020-10-20T16:29:23Z</updated>
<author>
<name>Abel Vesa</name>
<email>abel.vesa@nxp.com</email>
</author>
<published>2020-10-15T09:25:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b159c63d82ff8ffddc6c6f0eb881b113b36ecad7'/>
<id>urn:sha1:b159c63d82ff8ffddc6c6f0eb881b113b36ecad7</id>
<content type='text'>
According to the latest RM (see Table 5-1. Clock Root Table),
both usdhc root clocks have the parent order as follows:

000 - 25M_REF_CLK
001 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
101 - SYSTEM_PLL1_DIV3
110 - AUDIO_PLL2_CLK
111 - SYSTEM_PLL1_DIV8

So the audio_pll2_out and sys3_pll_out have to be swapped.

Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
Signed-off-by: Abel Vesa &lt;abel.vesa@nxp.com&gt;
Reported-by: Cosmin Stefan Stoica &lt;cosmin.stoica@nxp.com&gt;
Link: https://lore.kernel.org/r/1602753944-30757-1-git-send-email-abel.vesa@nxp.com
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: imx21: Remove clock driver</title>
<updated>2020-09-22T06:09:19Z</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2020-09-17T00:41:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=805837740d0142c38ab94b2269ca28da3890ae68'/>
<id>urn:sha1:805837740d0142c38ab94b2269ca28da3890ae68</id>
<content type='text'>
As i.MX21 support has been removed, get rid of its clock driver too.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: gate2: Fix a few typos</title>
<updated>2020-09-13T01:21:29Z</updated>
<author>
<name>Jonathan Neuschäfer</name>
<email>j.neuschaefer@gmx.net</email>
</author>
<published>2020-09-05T15:10:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b0772b4d95b1341d1f0f273894b999aa6b0916ba'/>
<id>urn:sha1:b0772b4d95b1341d1f0f273894b999aa6b0916ba</id>
<content type='text'>
A few words were misspelled in this comment.

Signed-off-by: Jonathan Neuschäfer &lt;j.neuschaefer@gmx.net&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: Fix and update kerneldoc</title>
<updated>2020-09-07T03:08:50Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2020-09-02T15:02:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=cca87e5cbd98897e06322a29a1dcac7a3c0f5ed1'/>
<id>urn:sha1:cca87e5cbd98897e06322a29a1dcac7a3c0f5ed1</id>
<content type='text'>
Fix and add missing kerneldoc to fix compile warnings like:

  drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw' not described in 'clk_pfd'
  drivers/clk/imx/clk-pllv3.c:53: warning: Function parameter or member 'ref_clock' not described in 'clk_pllv3'

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: fix i.MX7D peripheral clk mux flags</title>
<updated>2020-09-07T03:08:50Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-08-28T07:18:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=4757d2a3a32126be8bf5acb6eb293d0a1310dc1b'/>
<id>urn:sha1:4757d2a3a32126be8bf5acb6eb293d0a1310dc1b</id>
<content type='text'>
According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".

So we must have CLK_SET_PARENT_GATE flag to avoid glitch.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: fix composite peripheral flags</title>
<updated>2020-09-07T03:08:50Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-08-26T07:14:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=936c383673b9e3007432f17140ac62de53d87db9'/>
<id>urn:sha1:936c383673b9e3007432f17140ac62de53d87db9</id>
<content type='text'>
According to RM, for peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".

So we must have CLK_SET_PARENT_GATE flag to avoid glitch.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: Correct the memrepair clock on imx8mp</title>
<updated>2020-08-31T02:27:06Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2020-08-24T07:37:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f1859198509e4ddc93a24049f814fa0fcee0bfd8'/>
<id>urn:sha1:f1859198509e4ddc93a24049f814fa0fcee0bfd8</id>
<content type='text'>
The root clock slice at offset 0xbf80 should be memrepair
clock, so correct it. And this clock should be always on
to make sure the memory repair function can works well.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: Correct the root clk of media ldb on imx8mp</title>
<updated>2020-08-31T02:26:57Z</updated>
<author>
<name>Jacky Bai</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2020-08-24T07:37:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=afff77ce882dbd1a5fe0047df49b68a96cfe6d9b'/>
<id>urn:sha1:afff77ce882dbd1a5fe0047df49b68a96cfe6d9b</id>
<content type='text'>
The root clock slice at 0xbf00 is media_ldb clock,
not csi_phy2_ref, so correct it.

Signed-off-by: Jacky Bai &lt;ping.bai@nxp.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: vf610: Add CRC clock</title>
<updated>2020-08-23T02:08:35Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzk@kernel.org</email>
</author>
<published>2020-08-17T15:12:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0b8056106c02bef72b9d47524dc3c59ccf99124d'/>
<id>urn:sha1:0b8056106c02bef72b9d47524dc3c59ccf99124d</id>
<content type='text'>
Add the clock for CRC block allowing it to be enabled by consumers.

Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: imx: Explicitly include bits.h</title>
<updated>2020-08-22T12:36:57Z</updated>
<author>
<name>Anson Huang</name>
<email>Anson.Huang@nxp.com</email>
</author>
<published>2020-08-04T23:17:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7d6b5e4f2445728b9eca71f3fc21fd453d6b36b7'/>
<id>urn:sha1:7d6b5e4f2445728b9eca71f3fc21fd453d6b36b7</id>
<content type='text'>
It is better to explicitly include the required header file rather
then get it through some recursive include.

Signed-off-by: Anson Huang &lt;Anson.Huang@nxp.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
</content>
</entry>
</feed>
