<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/clk/mediatek/Makefile, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/clk/mediatek/Makefile?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/clk/mediatek/Makefile?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2019-09-09T16:37:30Z</updated>
<entry>
<title>clk: mediatek: Add MT6779 clock support</title>
<updated>2019-09-09T16:37:30Z</updated>
<author>
<name>mtk01761</name>
<email>wendell.lin@mediatek.com</email>
</author>
<published>2019-08-19T09:21:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=710774e048614c761a39a98e8d0fa75f688c83b6'/>
<id>urn:sha1:710774e048614c761a39a98e8d0fa75f688c83b6</id>
<content type='text'>
Add MT6779 clock support, include topckgen, apmixedsys,
infracfg, and subsystem clocks.

Signed-off-by: mtk01761 &lt;wendell.lin@mediatek.com&gt;
Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add audsys clock driver for MT8516</title>
<updated>2019-06-06T22:56:18Z</updated>
<author>
<name>Fabien Parent</name>
<email>fparent@baylibre.com</email>
</author>
<published>2019-05-02T12:18:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0fd4939ac100fe9e3645b846619d970ef6be2ade'/>
<id>urn:sha1:0fd4939ac100fe9e3645b846619d970ef6be2ade</id>
<content type='text'>
Add audsys clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent &lt;fparent@baylibre.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add clock driver for MT8516</title>
<updated>2019-04-25T21:36:58Z</updated>
<author>
<name>Fabien Parent</name>
<email>fparent@baylibre.com</email>
</author>
<published>2019-03-23T21:16:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=db077febb774b400cff461195106c1ea320497a4'/>
<id>urn:sha1:db077febb774b400cff461195106c1ea320497a4</id>
<content type='text'>
Add the clock driver for the MT8516 SoC.

Signed-off-by: Fabien Parent &lt;fparent@baylibre.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add MT8183 clock support</title>
<updated>2019-04-11T20:29:19Z</updated>
<author>
<name>Weiyi Lu</name>
<email>weiyi.lu@mediatek.com</email>
</author>
<published>2019-03-05T05:05:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=acddfc2c261b3653ab1c1b567a427299bac20d31'/>
<id>urn:sha1:acddfc2c261b3653ab1c1b567a427299bac20d31</id>
<content type='text'>
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.

Signed-off-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Tested-by: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Reviewed-by: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: Add new clkmux register API</title>
<updated>2019-04-11T20:12:40Z</updated>
<author>
<name>Owen Chen</name>
<email>owen.chen@mediatek.com</email>
</author>
<published>2019-03-05T05:05:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a3ae549917f1634f85c62984617521801505eb1e'/>
<id>urn:sha1:a3ae549917f1634f85c62984617521801505eb1e</id>
<content type='text'>
On both MT8183 &amp; MT6765, there add "set/clr" register for
each clkmux setting, and one update register to trigger value change.
It is designed to prevent read-modify-write racing issue.
The sw design need to add a new API to handle this hw change with
a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".

Signed-off-by: Owen Chen &lt;owen.chen@mediatek.com&gt;
Signed-off-by: Weiyi Lu &lt;weiyi.lu@mediatek.com&gt;
Reviewed-by: James Liao &lt;jamesjj.liao@mediatek.com&gt;
Reviewed-by: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Tested-by: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
[sboyd@kernel.org: Squash in flags=0 to silence warning]
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add clock support for MT7629 SoC</title>
<updated>2018-11-30T06:52:05Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-11-05T08:43:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3b5e748615e714711220b2a95d19bd25a037db09'/>
<id>urn:sha1:3b5e748615e714711220b2a95d19bd25a037db09</id>
<content type='text'>
Add all supported clocks exported from every susbystem found on MT7629 SoC.

Signed-off-by: Wenzhen Yu &lt;wenzhen.yu@mediatek.com&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add g3dsys support for MT2701 and MT7623</title>
<updated>2018-05-15T22:21:36Z</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2018-04-27T08:14:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a11ca689695118b367f59cc837f78c8fb414951d'/>
<id>urn:sha1:a11ca689695118b367f59cc837f78c8fb414951d</id>
<content type='text'>
Add clock driver support for g3dsys on MT2701 and MT7623, which is
providing essential clock gate and reset controller to Mali-450.

Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: add audsys support for MT2701</title>
<updated>2018-03-20T07:24:42Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-03-20T03:16:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b572f6393ee54bd4173a4313da8f2fb986a11089'/>
<id>urn:sha1:b572f6393ee54bd4173a4313da8f2fb986a11089</id>
<content type='text'>
Add clock driver support for MT2701 audsys.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built</title>
<updated>2018-01-10T21:41:15Z</updated>
<author>
<name>Sean Wang</name>
<email>sean.wang@mediatek.com</email>
</author>
<published>2018-01-05T08:14:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=bc27360b3c7aedfc385f7fc0527a42918bdeba51'/>
<id>urn:sha1:bc27360b3c7aedfc385f7fc0527a42918bdeba51</id>
<content type='text'>
Changes from v1-&gt;v2:
Add 'select RESET_CONTROLLER' under COMMON_CLK_MEDIATEK and enable
reset.c to be built when COMMON_CLK_MEDIATEK is selected. That should
be quite reasonable because the reset controller is tightly embedded
inside and exported from these clock subsystems. At least it can be found
on infracfg and pericfg subsystem that both are really fundamental block
lots of devices must depend on.

commit 74cb0d6dde8 ("clk: mediatek: fixup test-building of MediaTek clock
drivers") can let the build system looking into the directory where the
clock drivers resides and then allow test-building the drivers.

But the change also gives rise to certain incorrect behavior which is
reset.c being built even not depending on either COMPILE_TEST or
ARCH_MEDIATEK alternative dependency. To get rid of reset.c being built
unexpectedly on the other platforms, it would be a good change that the
file should be built depending on its own specific configuration rather
than just on generic RESET_CONTROLLER one.

Signed-off-by: Sean Wang &lt;sean.wang@mediatek.com&gt;
Cc: Jean Delvare &lt;jdelvare@suse.de&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux</title>
<updated>2017-11-18T04:04:24Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2017-11-18T04:04:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=fc35c1966e1372a21a88f6655279361e2f92713f'/>
<id>urn:sha1:fc35c1966e1372a21a88f6655279361e2f92713f</id>
<content type='text'>
Pull clk updates from Stephen Boyd:
 "We have two changes to the core framework this time around.

  The first being a large change that introduces runtime PM support to
  the clk framework. Now we properly call runtime PM operations on the
  device providing a clk when the clk is in use. This helps on SoCs
  where the clks provided by a device need something to be powered on
  before using the clks, like power domains or regulators. It also helps
  power those things down when clks aren't in use.

  The other core change is a devm API addition for clk providers so we
  can get rid of a bunch of clk driver remove functions that are just
  doing of_clk_del_provider().

  Outside of the core, we have the usual addition of clk drivers and
  smattering of non-critical fixes to existing drivers. The biggest diff
  is support for Mediatek MT2712 and MT7622 SoCs, but those patches
  really just add a bunch of data.

  By the way, we're trying something new here where we build the tree up
  with topic branches. We plan to work this into our workflow so that we
  don't step on each other's toes, and so the fixes branch can be merged
  on an as-needed basis.

  Summary:

  Core:
   - runtime PM support for clk providers
   - devm API for of_clk_add_hw_provider()

  New Drivers:
   - Mediatek MT2712 and MT7622
   - Renesas R-Car V3M SoC

  Updates:
   - runtime PM support for Samsung exynos5433/exynos4412 providers
   - removal of clkdev aliases on Samsung SoCs
   - convert clk-gpio to use gpio descriptors
   - various driver cleanups to match kernel coding style
   - Amlogic Video Processing Unit VPU and VAPB clks
   - sigma-delta modulation for Allwinner audio PLLs
   - Allwinner A83t Display clks
   - support for the second display unit clock on Renesas RZ/G1E
   - suspend/resume support for Renesas R-Car Gen3 CPG/MSSR
   - new clock ids for Rockchip rk3188 and rk3368 SoCs
   - various 'const' markings on clk_ops structures
   - RPM clk support on Qualcomm MSM8996/MSM8660 SoCs"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
  clk: stm32h7: fix test of clock config
  clk: pxa: fix building on older compilers
  clk: sunxi-ng: a83t: Fix i2c buses bits
  clk: ti: dra7-atl-clock: fix child-node lookups
  clk: qcom: common: fix legacy board-clock registration
  clk: uniphier: fix DAPLL2 clock rate of Pro5
  clk: uniphier: fix parent of miodmac clock data
  clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu'
  clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()
  clk: hi3660: fix incorrect uart3 clock freqency
  clk: kona-setup: Delete error messages for failed memory allocations
  ARC: clk: fix spelling mistake: "configurarion" -&gt; "configuration"
  clk: cdce925: remove redundant check for non-null parent_name
  clk: versatile: Improve sizeof() usage
  clk: versatile: Delete error messages for failed memory allocations
  clk: ux500: Improve sizeof() usage
  clk: ux500: Delete error messages for failed memory allocations
  clk: spear: Delete error messages for failed memory allocations
  clk: ti: Delete error messages for failed memory allocations
  clk: mmp: Adjust checks for NULL pointers
  ...
</content>
</entry>
</feed>
