wireguard-linux/drivers/clk/meson, branch jd/orphan-parallel

Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', 'clk-const' and 'clk-mmp2' into clk-next

2020-10-20T18:47:02Z

* clk-semicolon: clk: meson: use semicolons rather than commas to separate statements clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements clk: uniphier: use semicolons rather than commas to separate statements * clk-axi-clkgen: clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers * clk-qoriq: clk: qoriq: modify MAX_PLL_DIV to 32 * clk-baikal: clk: baikal-t1: Mark Ethernet PLL as critical * clk-const: clk: pxa: Constify static struct clk_ops * clk-mmp2: clk: mmp2: Fix the display clock divider base

clk: meson: use semicolons rather than commas to separate statements

2020-10-14T00:43:07Z

Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // @@ expression e1,e2; @@ e1 -, +; e2 ... when any // Signed-off-by: Julia Lawall Link: https://lore.kernel.org/r/1601233948-11629-11-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd

clk: meson: make shipped controller configurable

2020-09-10T09:47:33Z

Add the necessary bits so unnecessary amlogic clock controllers can be compiled out. This allows to save a few kB when necessary. Signed-off-by: Jerome Brunet Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20200828154735.435374-1-jbrunet@baylibre.com

clk: meson: g12a: mark fclk_div2 as critical

2020-08-29T14:16:18Z

On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2 seems to be necessary for the system to operate correctly as well. Typically, the clock also gets chosen by the eMMC peripheral. This probably masked the problem so far. However, when booting from a SD card the clock seems to get disabled which leads to a system freeze. Let's mark this clock as critical, fixing boot from SD card on G12b platforms. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Stefan Agner Signed-off-by: Jerome Brunet Tested-by: Anand Moon Cc: Marek Szyprowski Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch

clk: meson: axg-audio: fix g12a tdmout sclk inverter

2020-08-17T13:58:12Z

Fix the tdmout inverter of the g12a and following SoC families. This inverter is special and needs two bits to be the inverse of each other for the inverter to operate properly. Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support") Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200729154359.1983085-4-jbrunet@baylibre.com

clk: meson: axg-audio: separate axg and g12a regmap tables

2020-08-17T13:58:09Z

There are more differences than what we initially thought. Let's keeps things clear and separate the axg and g12a regmap tables of the audio clock controller. Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200729154359.1983085-3-jbrunet@baylibre.com

clk: meson: add sclk-ws driver

2020-08-17T13:58:02Z

This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com

Merge branch 'clk-amlogic' into clk-next

2020-07-21T08:01:11Z

* clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs

Replace HTTP links with HTTPS ones: Common CLK framework

2020-07-11T00:15:34Z

Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de Signed-off-by: Stephen Boyd

clk: meson: meson8b: add the vclk2_en gate clock

2020-07-09T09:37:44Z

HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However, the GXBB driver defines this bit as a gate called "vclk2" and in the 3.10 kernel GPL code dump the following line can found: WRITE_LCD_CBUS_REG_BITS(HHI_VIID_CLK_CNTL, 0, 19, 1); //disable vclk2_en Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller to complete the VCLK2 clock tree. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200629203904.2989007-3-martin.blumenstingl@googlemail.com