wireguard-linux/drivers/clk/meson, branch update-toolchain

clk: meson: add missing MODULE_DESCRIPTION() macros

2024-06-14T07:29:41Z

Add the missing MODULE_DESCRIPTION() in the Amlogic clock modules missing it. Reported-by: Jeff Johnson Closes: https://lore.kernel.org/linux-clk/964210f1-671f-4ecc-bdb7-3cf53089c327@quicinc.com Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240611133512.341817-1-jbrunet@baylibre.com Signed-off-by: Jerome Brunet

clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL

2024-06-10T10:16:01Z

When dealing with certain PLLs, it is necessary to avoid modifying them if they have already been initialized by lower levels. For instance, in the A1 SoC Family, the sys_pll is enabled as the parent for the cpuclk, and it cannot be disabled during the initialization sequence. Therefore, initialization phase must be skipped. Signed-off-by: Dmitry Rokosov Link: https://lore.kernel.org/r/20240515185103.20256-2-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet

clk: meson: c3: add c3 clock peripherals controller driver

2024-06-04T08:38:32Z

Add the C3 peripherals clock controller driver in the C3 SoC family. [jbrunet: fix Kconfig select order and probe function name] Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240522082727.3029656-6-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: c3: add support for the C3 SoC PLL clock

2024-06-04T08:38:16Z

Add the C3 PLL clock controller driver for the Amlogic C3 SoC family. [jbrunet: fixed probe function name] Co-developed-by: Chuan Liu Signed-off-by: Chuan Liu Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: s4: fix pwm_j_div parent clock

2024-06-03T10:39:33Z

Update peripherals pwm_j_div's parent clock to pwm_j_mux Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller") Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240516071612.2978201-1-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: s4: fix fixed_pll_dco clock

2024-06-03T10:29:37Z

The fixed_pll_dco output frequency is not accurate, add frac factor for fixed_pll_dco clk to fix it. Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller") Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com Signed-off-by: Jerome Brunet

clk: meson: s4: fix module autoloading

2024-05-03T12:27:32Z

Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Clocks are considered core components, so usually they are built-in, however these can be built and used as modules on some generic kernel. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20240410155406.224128-1-krzk@kernel.org Signed-off-by: Jerome Brunet

clk: meson: fix module license to GPL only

2024-04-10T07:47:18Z

Fix the checkpatch warning: WARNING: Prefer "GPL" over "GPL v2" - see commit bf7fbeeae6db ("module: Cure the MODULE_LICENSE "GPL" vs. "GPL v2" bogosity") Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20240408-amlogic-v6-9-upstream-fix-clk-module-license-v1-1-366ddc0f3db9@linaro.org Signed-off-by: Jerome Brunet

clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF

2024-04-10T07:46:21Z

In order to setup the DSI clock, let's make the unused VCLK2 clock path configuration via CCF. The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel vclk2 and vclk2_div uses the newly introduced vclk regmap driver to handle the enable and reset bits. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT or manually set by the display driver at some point. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the DSI bitclock is the reference base clock to calculate the vclk2_div value when pixel clock is set on the cts_encl endpoint. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet

clk: meson: add vclk driver

2024-04-10T07:46:21Z

The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet