wireguard-linux/drivers/clk/qcom, branch jd/orphan-parallel

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2020-10-22T19:53:28Z

Pull clk updates from Stephen Boyd: "This contains no changes to the core framework. It is a collection of various clk driver updates. The biggest driver updates in terms of lines of code is the Allwinner driver, closely followed by the Qualcomm and Mediatek drivers. All of those hit high because we add so many lines of clk data. Coming in fourth place is i.MX which also adds a bunch of clk data. This accounts for the new driver additions this time around. Otherwise the patches are lots of little cleanups and fixes for various clk drivers that have baked in linux-next for a while. I suppose one highlight or theme is that more clk drivers are being updated to work as modules, which is interesting to see such critical SoC infrastructure work as a loadable module. New Drivers: - Support qcom SM8150/SM8250 video and display clks - Support Mediatek MT8167 clks - Add clock for CRC block found on vf610 SoCs - Add support for the Renesas R-Car V3U (R8A779A0) SoC - Add support for the VSP for Resizing clock on Renesas RZ/G1H - Support Allwinner A100 SoC clks Removed Drivers: - Remove i.MX21 clock driver, as i.MX21 platform support is being dropped Updates: - Change how qcom's display port clks work - Small non-critical fixes for TI clk driver - Remove various unused variables in clk drivers - Allow Rockchip clk driver to be a module - Remove most __clk_lookup() calls in Samsung drivers (yay!) - Support building i.MX ARMv8 platforms clock driver as module - Some kerneldoc fixes here and there - A couple of minor i.MX clk data corrections - Update audio clock inverter and fdiv2 flag on Amlogic g12 - Make amlogic clk drivers configurable in Kconfig - Fix Renesas VSP clock names to match corrected hardware documentation - Sigma-delta modulation on Allwinner R40 - Various fixes for at91 clk driver - Use semicolons instead of commas in some places - Mark some variables const so they can move to RO memory" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits) clk: imx8mq: Fix usdhc parents order clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on clk: Restrict CLK_HSDK to ARC_SOC_HSDK clk: at91: sam9x60: support only two programmable clocks clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL clk: ingenic: Use readl_poll_timeout instead of custom loop clk: ingenic: Use to_clk_info() macro for all clocks clk: bcm2835: add missing release if devm_clk_hw_register fails clk: at91: clk-sam9x60-pll: remove unused variable clk: at91: clk-main: update key before writing AT91_CKGR_MOR clk: at91: remove the checking of parent_name clk: clk-prima2: fix return value check in prima2_clk_init() clk: mmp2: Fix the display clock divider base clk: pxa: Constify static struct clk_ops clk: baikal-t1: Mark Ethernet PLL as critical clk: qoriq: modify MAX_PLL_DIV to 32 clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers ...

clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on

2020-10-20T16:28:55Z

If the GDSC is enabled out of boot but doesn't have the retain ff bit set we will get confusing results where the registers that are powered by the GDSC lose their contents on the first power off of the GDSC but thereafter they retain their contents. This is because gdsc_init() fails to make sure the RETAIN_FF bit is set when it probes the GDSC the first time and thus powering off the GDSC causes the register contents to be reset. We do set the RETAIN_FF bit the next time we power on the GDSC, see gdsc_enable(), so that subsequent GDSC power off's don't lose register contents state. Forcibly set the bit at device probe time so that the kernel's assumed view of the GDSC is consistent with the state of the hardware. This fixes a problem where the audio PLL doesn't work on sc7180 when the bootloader leaves the lpass_core_hm GDSC enabled at boot (e.g. to make a noise) but critically doesn't set the RETAIN_FF bit. Cc: Douglas Anderson Cc: Taniya Das Cc: Rajendra Nayak Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20201017020137.1251319-1-sboyd@kernel.org Reviewed-by: Taniya Das Reviewed-by: Douglas Anderson Tested-by: Douglas Anderson

clk: qcom: Add display clock controller driver for SM8150 and SM8250

2020-10-14T01:18:06Z

Add support for the display clock controller found on SM8150 and SM8250. Signed-off-by: Jonathan Marek Tested-by: Dmitry Baryshkov (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca Signed-off-by: Stephen Boyd

clk: qcom: add video clock controller driver for SM8250

2020-10-14T01:05:04Z

Add support for the video clock controller found on SM8250 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200923160635.28370-6-jonathan@marek.ca Signed-off-by: Stephen Boyd

clk: qcom: add video clock controller driver for SM8150

2020-10-14T01:05:04Z

Add support for the video clock controller found on SM8150 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200923160635.28370-5-jonathan@marek.ca Signed-off-by: Stephen Boyd

clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs

2020-10-14T01:04:36Z

This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005145855.149206-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd

clk/qcom: fix spelling typo

2020-10-13T23:32:27Z

Modify the comment typo: "compliment" -> "complement". Signed-off-by: Wang Qing Link: https://lore.kernel.org/r/1600930506-394-1-git-send-email-wangqing@vivo.com Signed-off-by: Stephen Boyd

clk: qcom: gcc-sdm660: Fix wrong parent_map

2020-09-22T19:06:19Z

This was likely overlooked while porting the driver upstream. Reported-by: Pavel Dubrova Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20200922120909.97203-1-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd

clk: qcom: dispcc: Update DP clk ops for phy design

2020-09-22T18:51:08Z

The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk. This function should return the rate that can be achieved by the pixel clk in 'struct clk_rate_request::rate' and match the logic similar to what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead the code merely bubbles the rate request up to the parent of the pixel clk and doesn't try to do a rational approximation of the rate that would be achieved by picking some m/n value for the RCG. Let's change this logic so that we can assume the parent clk frequency is fixed (it is because it's the VCO of the DP PLL that is configured based on the link rate) and so that we can calculate what the m/n value will be and adjust the req->rate appropriately. Cc: Jeykumar Sankaran Cc: Chandan Uddaraju Cc: Vara Reddy Cc: Tanmay Shah Cc: Bjorn Andersson Cc: Manu Gautam Cc: Sandeep Maheswaram Cc: Douglas Anderson Cc: Sean Paul Cc: Stephen Boyd Cc: Jonathan Marek Cc: Dmitry Baryshkov Cc: Rob Clark Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20200916231202.3637932-10-swboyd@chromium.org Signed-off-by: Stephen Boyd

clk: qcom: gcc-msm8939: remove defined but not used variables

2020-09-22T18:50:23Z

This addresses the following gcc warning with "make W=1": drivers/clk/qcom/gcc-msm8939.c:610:32: warning: ‘gcc_xo_gpll6_gpll0a_map’ defined but not used [-Wunused-const-variable=] static const struct parent_map gcc_xo_gpll6_gpll0a_map[] = { ^~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gcc-msm8939.c:598:32: warning: ‘gcc_xo_gpll6_gpll0_map’ defined but not used [-Wunused-const-variable=] static const struct parent_map gcc_xo_gpll6_gpll0_map[] = { ^~~~~~~~~~~~~~~~~~~~~~ Reported-by: Hulk Robot Signed-off-by: Jason Yan Link: https://lore.kernel.org/r/20200911013722.1459387-1-yanaijie@huawei.com Reviewed-by: Bjorn Andersson Signed-off-by: Stephen Boyd