wireguard-linux/drivers/clk/qcom, branch update-toolchain

of: remove internal arguments from of_property_for_each_u32()

2024-07-25T11:53:47Z

The of_property_for_each_u32() macro needs five parameters, two of which are primarily meant as internal variables for the macro itself (in the for() clause). Yet these two parameters are used by a few drivers, and this can be considered misuse or at least bad practice. Now that the kernel uses C11 to build, these two parameters can be avoided by declaring them internally, thus changing this pattern: struct property *prop; const __be32 *p; u32 val; of_property_for_each_u32(np, "xyz", prop, p, val) { ... } to this: u32 val; of_property_for_each_u32(np, "xyz", val) { ... } However two variables cannot be declared in the for clause even with C11, so declare one struct that contain the two variables we actually need. As the variables inside this struct are not meant to be used by users of this macro, give the struct instance the noticeable name "_it" so it is visible during code reviews, helping to avoid new code to use it directly. Most usages are trivially converted as they do not use those two parameters, as expected. The non-trivial cases are: - drivers/clk/clk.c, of_clk_get_parent_name(): easily doable anyway - drivers/clk/clk-si5351.c, si5351_dt_parse(): this is more complex as the checks had to be replicated in a different way, making code more verbose and somewhat uglier, but I refrained from a full rework to keep as much of the original code untouched having no hardware to test my changes All the changes have been build tested. The few for which I have the hardware have been runtime-tested too. Reviewed-by: Andre Przywara # drivers/clk/sunxi/clk-simple-gates.c, drivers/clk/sunxi/clk-sun8i-bus-gates.c Acked-by: Bartosz Golaszewski # drivers/gpio/gpio-brcmstb.c Acked-by: Nicolas Ferre # drivers/irqchip/irq-atmel-aic-common.c Acked-by: Jonathan Cameron # drivers/iio/adc/ti_am335x_adc.c Acked-by: Uwe Kleine-König # drivers/pwm/pwm-samsung.c Acked-by: Richard Leitner # drivers/usb/misc/usb251xb.c Acked-by: Mark Brown # sound/soc/codecs/arizona.c Reviewed-by: Richard Fitzgerald # sound/soc/codecs/arizona.c Acked-by: Michael Ellerman # arch/powerpc/sysdev/xive/spapr.c Acked-by: Stephen Boyd # clk Signed-off-by: Luca Ceresoli Acked-by: Lee Jones Link: https://lore.kernel.org/r/20240724-of_property_for_each_u32-v3-1-bea82ce429e2@bootlin.com Signed-off-by: Rob Herring (Arm)

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2024-07-19T19:16:28Z

Pull clk updates from Stephen Boyd: "This a large collection of clk driver updates and a handful of new SoC clk driver support. We have the usual Qualcomm clk drivers, along with clk drivers for the Sophgo and T-Head vendors, all to support some new SoCs. Nothing in particular stands out to me in the updates. There's the interconnect clk driver which exposes clks as interconnects, crossing subsystems. There's a bunch of janitorial things that are improving drivers in general like kmemdup_array() or fixing error paths. But overall the updates look normal to fix the description data which is usually the stuff that's wrong and/or untested. Core: - Skip gate basic type KUnit tests on s390 due to lack of MMIO emulation New Drivers: - AP sub-system clock controller in the T-Head TH1520 - Sophgo Sophon sg2042 clk driver - Qualcomm SM7150 camera, display and video clk drivers - Qualcomm QCM2290 GPU clk driver - Qualcomm QCS8386/QCS8084 NSS clk driver - Qualcomm SM8650 camera and video drivers Updates: - Add reset support to Airoha EN7581 clk driver - Add MODULE_DESCRIPTIONs to various clk drivers - Introduce helper logic to expose clock controllers as simple interconnect providers - Use the interconnect helper above on Qualcomm ipq9574 - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm X1Elite - Improve error handling in Qualcomm kpss-xcc driver - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const - Export more clocks for Rockchip rk3128 peripherals - Convert Rockchip clk drivers to use kmemdup_array() - Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers - Make qcom_cc_really_probe() take a struct device to allow reuse in non-platform-drivers - Introduce prepare-only branch clock ops in the qcom clk driver to support clocks on buses that take locks - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs - Support Qualcomm Huayra 2290 alpha PLL - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match HS200 support - Add missing PCIe PIPE clocks on Qualcomm IPQ9574 - Fix various configurations and properties in the Qualcomm SA8775P, X1E80100 and SM7280 drivers - Park Qualcomm SM8350 GPU RCGs on XO while disabled - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol - exynos-clkout: Remove usage of of_device_id table as .of_match_table, because the driver is instantiated as MFD cell, not as standalone platform driver. Populated .of_match_table confused people few times to convert the code to device_get_match_data(), which broke the driver - Mark one Samsung UFS clock as critical, because having it off stops the system from shutdown - Use kmemdup_array() when applicable - Remove unused 'struct gates_data' from old sunxi driver library - Add GPADC clock and reset for Allwinner H616 - Minor Amlogic S4 clock fixes - DT bindings Yaml conversion of the Amlogic AXG audio controller - Amlogic C3 clock controllers support - Amlogic clk flag added to skip init of already enabled PLLs and avoid relocking - Amlogic A1 DT bindings updates for system pll support - Add missing MODULE_DESCRIPTION where necessary - Remove obsolete clock DT binding header files - Add Battery Backup (VBATTB) and I2C clocks, resets, and power domains on Renesas RZ/G3S - Add audio clocks on Renesas R-Car V4M - Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits) clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate() clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id() clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate() clk: sunxi-ng r40: Constify struct regmap_config clk: en7523: fix rate divider for slic and spi clocks clk: lpc32xx: Constify struct regmap_config clk: xilinx: Constify struct regmap_config clk: en7523: Remove PCIe reset open drain configuration for EN7581 clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC clk: en7523: Add reset-controller support for EN7581 SoC dt-bindings: clock: airoha: Add reset support to EN7581 clock binding dt-bindings: clock: mediatek: Document reset cells for MT8188 sys clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys dt-bindings: clock: sprd,sc9860-clk: convert to YAML dt-bindings: clock: qoriq-clock: convert to yaml format clk: qcom: Park shared RCGs upon registration clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks ...

Merge tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2024-07-16T18:43:51Z

Pull SoC dt updates from Arnd Bergmann: "The devicetree updates are fairly well spread out across platforms, with Qualcomm making up about a third of the total. There are three new SoCs in existing product families this: - NXP i.MX95 is a variant of i.MX93, now with six Cortex-A55 cores instead of just two as well as a GPU and more high-speed I/O devices. - Qualcomm QCS8550 is a variant of SM8550 for IOT devices - Airoha EN7581 is a 10G-PON network chip and related to the MT7981 Wireless router chip from its parent Mediatek. In total there are 58 new machines, including four riscv boards and eight for 32-bit arm. The most exciting new addition is probably a pair of laptops based on the Qualcomm x1e80100 (Snapdragon X1 Elite) chip, the Asus Vivobook S15 and the Lenovo Yoga Slim7x. Other noteworthy new additions are: - A total of 20 Qualcomm based machines, mostly Android devices from Samsung, Motorola and LG, as well as a wireless router and some reference designs - Six NXP i.MX based machines, mostly industrial boards along with some reference designs - Mediatek sees some interesting Filogic based routers including the "OpenWRT One", a few new Chromebooks as well as single-board computers. - Four machines from Solidrun based on Marvell cn913x, replacing the older Armada 8000 based counterparts - The four Amlogic machines are all set top boxes or reference designs for them - The nine new Rockchips machines are mostly single-board computers including some interesting ones based on the rk3588 chip like the ROCK 5 ITX board and the CM3588 with its four NVMe slots - The RISC-V boards are all single-board computers based on Starfive JH7110, Microchip MPFS and Allwinner D1, which all had similar boards already There are also a lot of updates to already supported machines, notably for the TI K3, Rockchips, Freescale and of course Qualcomm platforms" * tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (846 commits) arm64: dts: allwinner: h616: add crypto engine node riscv: dts: add clock generator for Sophgo SG2042 SoC arm64: dts: rockchip: Add Xunlong Orange Pi 3B dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B arm64: dts: rockchip: Add Radxa ROCK 3B dt-bindings: arm: rockchip: Add Radxa ROCK 3B mailmap: Update Luca Weiss's email address ARM: dts: ixp4xx: nslu2: beeper uses PWM arm64: dts: rockchip: add ROCK 5 ITX board dt-bindings: arm: rockchip: Add ROCK 5 ITX board arm64: dts: rockchip: Add dma-names to uart1 on Pine64 rk3566 devices arm64: dts: rockchip: Add avdd supplies to hdmi on rock64 arm64: dts: qcom: msm8916-lg-c50: add initial dts for LG Leon LTE arm64: dts: qcom: msm8916-lg-m216: Add initial device tree dt-bindings: arm: qcom: Add msm8916 based LG devices ARM: dts: qcom: msm8960: correct memory base arm64: dts: qcom: ipq9574: Add icc provider ability to gcc dt-bindings: interconnect: Add Qualcomm IPQ9574 support arm64: dts: qcom: sm8150: Add video clock controller node arm64: dts: qcom: pm6150: Add vibrator ...

Merge tag 'pmdomain-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm

2024-07-16T00:44:59Z

Pull pmdomain updates from Ulf Hansson: "pmdomain core: - Add support for HW-managed devices pmdomain providers: - amlogic: Add support for the A5 and the A4 power domains - arm: Enable system wakeups for the SCMI PM domain - qcom/clk: Add HW-mode callbacks to allow switching of GDSC mode pmdomain consumers: - qcom/media/venus: Enable support for switching GDSC HW-mode on V6" * tag 'pmdomain-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: pmdomain: amlogic: Constify struct meson_secure_pwrc_domain_desc venus: pm_helpers: Use dev_pm_genpd_set_hwmode to switch GDSC mode on V6 clk: qcom: videocc: Use HW_CTRL_TRIGGER for SM8250, SC7280 vcodec GDSC's clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode PM: domains: Add the domain HW-managed mode to the summary PM: domains: Allow devices attached to genpd to be managed by HW pmdomain: amlogic: Add support for A5 power domains controller dt-bindings: power: add Amlogic A5 power domains pmdomain: amlogic: add missing MODULE_DESCRIPTION() macros pmdomain: arm: scmi_pm_domain: set flag GENPD_FLAG_ACTIVE_WAKEUP pmdomain: renesas: rmobile-sysc: Use for_each_child_of_node_scoped() pmdomain: core: Use genpd_is_irq_safe() helper pmdomain: amlogic: Add support for A4 power domains controller dt-bindings: power: add Amlogic A4 power domains

Merge tag 'qcom-clk-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

2024-07-09T19:54:12Z

Pull more qcom clk driver updates from Bjorn Andersson: - Introduces helper logic to expose clock controllers as simple interconnect providers - Use the interconnect helper above on Qualcomm ipq9574 - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm X1Elite. - Improve error handling in Qualcomm kpss-xcc driver - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const * tag 'qcom-clk-for-6.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks clk: qcom: common: Add interconnect clocks support interconnect: icc-clk: Add devm_icc_clk_register interconnect: icc-clk: Specify master/slave ids dt-bindings: clock: qcom: Add AHB clock for SM8150 clk: qcom: gcc-x1e80100: Set parent rate for USB3 sec and tert PHY pipe clks dt-bindings: interconnect: Add Qualcomm IPQ9574 support clk: qcom: kpss-xcc: Return of_clk_add_hw_provider to transfer the error clk: qcom: lpasscc-sc8280xp: Constify struct regmap_config

clk: qcom: videocc: Use HW_CTRL_TRIGGER for SM8250, SC7280 vcodec GDSC's

2024-07-09T10:59:58Z

For Venus V6 variant SoCs(sm8250, sc7280), the venus driver uses the newly introduced dev_pm_genpd_set_hwmode() API to switch the vcodec GDSC to HW/SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag for vcodec GDSC's on sm8250, sc7280 to register the set_hwmode_dev & get_hwmode_dev callbacks for vcodec GDSC and allow the GDSC mode to be changed using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona Signed-off-by: Abel Vesa Reviewed-by: Taniya Das Acked-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240624044809.17751-5-quic_jkona@quicinc.com Signed-off-by: Ulf Hansson

clk: qcom: gdsc: Add set and get hwmode callbacks to switch GDSC mode

2024-07-09T10:59:58Z

Some GDSC client drivers require the GDSC mode to be switched dynamically to HW mode at runtime to gain the power benefits. Typically such client drivers require the GDSC to be brought up in SW mode initially to enable the required dependent clocks and configure the hardware to proper state. Once initial hardware set up is done, they switch the GDSC to HW mode to save power. At the end of usecase, they switch the GDSC back to SW mode and disable the GDSC. Introduce HW_CTRL_TRIGGER flag to register the set_hwmode_dev and get_hwmode_dev callbacks for GDSC's whose respective client drivers require the GDSC mode to be switched dynamically at runtime using dev_pm_genpd_set_hwmode() API. Signed-off-by: Jagadeesh Kona Signed-off-by: Abel Vesa Reviewed-by: Bryan O'Donoghue Reviewed-by: Taniya Das Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240624044809.17751-4-quic_jkona@quicinc.com Signed-off-by: Ulf Hansson

clk: qcom: Park shared RCGs upon registration

2024-07-08T18:31:57Z

There's two problems with shared RCGs. The first problem is that they incorrectly report the parent after commit 703db1f5da1e ("clk: qcom: rcg2: Cache CFG register updates for parked RCGs"). That's because the cached CFG register value needs to be populated when the clk is registered. clk_rcg2_shared_enable() writes the cached CFG register value 'parked_cfg'. This value is initially zero due to static initializers. If a driver calls clk_enable() before setting a rate or parent, it will set the parent to '0' which is (almost?) always XO, and may not reflect the parent at registration. In the worst case, this switches the RCG from sourcing a fast PLL to the slow crystal speed. The second problem is that the force enable bit isn't cleared. The force enable bit is only used during parking and unparking of shared RCGs. Otherwise it shouldn't be set because it keeps the RCG enabled even when all the branches on the output of the RCG are disabled (the hardware has a feedback mechanism so that any child branches keep the RCG enabled when the branch enable bit is set). This problem wastes power if the clk is unused, and is harmful in the case that the clk framework disables the parent of the force enabled RCG. In the latter case, the GDSC the shared RCG is associated with will get wedged if the RCG's source clk is disabled and the GDSC tries to enable the RCG to do "housekeeping" while powering on. Both of these problems combined with incorrect runtime PM usage in the display driver lead to a black screen on Qualcomm sc7180 Trogdor chromebooks. What happens is that the bootloader leaves the 'disp_cc_mdss_rot_clk' enabled and the 'disp_cc_mdss_rot_clk_src' force enabled and parented to 'disp_cc_pll0'. The mdss driver probes and runtime suspends, disabling the mdss_gdsc which uses the 'disp_cc_mdss_rot_clk_src' for "housekeeping". The 'disp_cc_mdss_rot_clk' is disabled during late init because the clk is unused, but the parent 'disp_cc_mdss_rot_clk_src' is still force enabled because the force enable bit was never cleared. Then 'disp_cc_pll0' is disabled because it is also unused. That's because the clk framework believes the parent of the RCG is XO when it isn't. A child device of the mdss device (e.g. DSI) runtime resumes mdss which powers on the mdss_gdsc. This wedges the GDSC because 'disp_cc_mdss_rot_clk_src' is parented to 'disp_cc_pll0' and that PLL is off. With the GDSC wedged, mdss_runtime_resume() tries to enable 'disp_cc_mdss_mdp_clk' but it can't because the GDSC has wedged all the clks associated with the GDSC causing clks to stay stuck off. This leads to the following warning seen at boot and a black screen because the display driver fails to probe. disp_cc_mdss_mdp_clk status stuck at 'off' WARNING: CPU: 1 PID: 81 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x114/0x168 Modules linked in: CPU: 1 PID: 81 Comm: kworker/u16:4 Not tainted 6.7.0-g0dd3ee311255 #1 f5757d475795053fd2ad52247a070cd50dd046f2 Hardware name: Google Lazor (rev1 - 2) with LTE (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : clk_branch_toggle+0x114/0x168 lr : clk_branch_toggle+0x110/0x168 sp : ffffffc08084b670 pmr_save: 00000060 x29: ffffffc08084b680 x28: ffffff808006de00 x27: 0000000000000001 x26: ffffff8080dbd4f4 x25: 0000000000000000 x24: 0000000000000000 x23: 0000000000000000 x22: ffffffd838461198 x21: ffffffd838007997 x20: ffffffd837541d5c x19: 0000000000000001 x18: 0000000000000004 x17: 0000000000000000 x16: 0000000000000010 x15: ffffffd837070fac x14: 0000000000000003 x13: 0000000000000004 x12: 0000000000000001 x11: c0000000ffffdfff x10: ffffffd838347aa0 x9 : 08dadf92e516c000 x8 : 08dadf92e516c000 x7 : 0000000000000000 x6 : 0000000000000027 x5 : ffffffd8385a61f2 x4 : 0000000000000000 x3 : ffffffc08084b398 x2 : ffffffc08084b3a0 x1 : 00000000ffffdfff x0 : 00000000fffffff0 Call trace: clk_branch_toggle+0x114/0x168 clk_branch2_enable+0x24/0x30 clk_core_enable+0x5c/0x1c8 clk_enable+0x38/0x58 clk_bulk_enable+0x40/0xb0 mdss_runtime_resume+0x68/0x258 pm_generic_runtime_resume+0x30/0x44 __genpd_runtime_resume+0x30/0x80 genpd_runtime_resume+0x124/0x214 __rpm_callback+0x7c/0x15c rpm_callback+0x30/0x88 rpm_resume+0x390/0x4d8 rpm_resume+0x43c/0x4d8 __pm_runtime_resume+0x54/0x98 __device_attach+0xe0/0x170 device_initial_probe+0x1c/0x28 bus_probe_device+0x48/0xa4 device_add+0x52c/0x6fc mipi_dsi_device_register_full+0x104/0x1a8 devm_mipi_dsi_device_register_full+0x28/0x78 ti_sn_bridge_probe+0x1dc/0x2bc auxiliary_bus_probe+0x4c/0x94 really_probe+0xf8/0x270 __driver_probe_device+0xa8/0x130 driver_probe_device+0x44/0x104 __device_attach_driver+0xa4/0xcc bus_for_each_drv+0x94/0xe8 __device_attach+0xf8/0x170 device_initial_probe+0x1c/0x28 bus_probe_device+0x48/0xa4 deferred_probe_work_func+0x9c/0xd8 Fix these problems by parking shared RCGs at boot. This will properly initialize the parked_cfg struct member so that the parent is reported properly and ensure that the clk won't get stuck on or off because the RCG is parented to the safe source (XO). Fixes: 703db1f5da1e ("clk: qcom: rcg2: Cache CFG register updates for parked RCGs") Reported-by: Stephen Boyd Closes: https://lore.kernel.org/r/1290a5a0f7f584fcce722eeb2a1fd898.sboyd@kernel.org Closes: https://issuetracker.google.com/319956935 Reported-by: Laura Nao Closes: https://lore.kernel.org/r/20231218091806.7155-1-laura.nao@collabora.com Cc: Bjorn Andersson Cc: Dmitry Baryshkov Cc: Douglas Anderson Cc: Taniya Das Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20240502224703.103150-1-swboyd@chromium.org Reviewed-by: Douglas Anderson Tested-by: Nícolas F. R. A. Prado Signed-off-by: Stephen Boyd

clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks

2024-07-08T16:40:57Z

Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Signed-off-by: Varadarajan Narayanan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240430064214.2030013-6-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson

clk: qcom: common: Add interconnect clocks support

2024-07-08T16:40:57Z

Unlike MSM platforms that manage NoC related clocks and scaling from RPM, IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for accessing the peripheral controllers present on these NoCs. Though exposing these as normal clocks would work, having a minimalistic interconnect driver to handle these clocks would make it consistent with other Qualcomm platforms resulting in common code paths. This is similar to msm8996-cbf's usage of icc-clk framework. Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20240430064214.2030013-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson