wireguard-linux/drivers/clk/sprd/gate.c, branch jd/unified-crypt-queueWireGuard for the Linux kernelhttps://git.zx2c4.com/wireguard-linux/atom/drivers/clk/sprd/gate.c?h=jd%2Funified-crypt-queue2020-03-25T02:03:56Zclk: sprd: add gate for pll clocks2020-03-25T02:03:56ZXiaolong Zhangxiaolong.zhang@unisoc.com2020-03-04T07:27:24Zurn:sha1:187e5cd2d133771e978e7e4ea6aa684dfd1ce6ab
Some sprd's gate clocks are used to the switch of pll, which
need to wait a certain time for stable after being enabled.
Signed-off-by: Xiaolong Zhang <xiaolong.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Link: https://lkml.kernel.org/r/20200304072730.9193-2-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: sprd: add gate clock support2017-12-21T23:00:51ZChunyan Zhangchunyan.zhang@spreadtrum.com2017-12-07T12:57:06Zurn:sha1:cdb09f67a2b58f0e0a2764243cf2c912c158f0a6
Some clocks on the Spreadtrum's SoCs are just simple gates. Add
support for those clocks.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>