<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/crypto/hisilicon/Kconfig, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/crypto/hisilicon/Kconfig?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/crypto/hisilicon/Kconfig?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-03T04:37:26Z</updated>
<entry>
<title>crypto: hisilicon - Fix build error</title>
<updated>2020-04-03T04:37:26Z</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2020-03-30T08:36:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b5f13031cd8da1b8f1e277d03a773dc46f7cff11'/>
<id>urn:sha1:b5f13031cd8da1b8f1e277d03a773dc46f7cff11</id>
<content type='text'>
When UACCE is m, CRYPTO_DEV_HISI_QM cannot be built-in.
But CRYPTO_DEV_HISI_QM is selected by CRYPTO_DEV_HISI_SEC2
and CRYPTO_DEV_HISI_HPRE unconditionally, which may leads this:

drivers/crypto/hisilicon/qm.o: In function 'qm_alloc_uacce':
drivers/crypto/hisilicon/qm.c:1579: undefined reference to 'uacce_alloc'

Add Kconfig dependency to enforce usable configurations.

Fixes: 47c16b449921 ("crypto: hisilicon - qm depends on UACCE")
Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - qm depends on UACCE</title>
<updated>2020-03-06T01:28:24Z</updated>
<author>
<name>Hongbo Yao</name>
<email>yaohongbo@huawei.com</email>
</author>
<published>2020-02-27T07:12:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=47c16b4499213b8173ad3c033a41d850c6fa0e7c'/>
<id>urn:sha1:47c16b4499213b8173ad3c033a41d850c6fa0e7c</id>
<content type='text'>
If UACCE=m and CRYPTO_DEV_HISI_QM=y, the following error
is seen while building qm.o:

drivers/crypto/hisilicon/qm.o: In function `hisi_qm_init':
(.text+0x23c6): undefined reference to `uacce_alloc'
(.text+0x2474): undefined reference to `uacce_remove'
(.text+0x286b): undefined reference to `uacce_remove'
drivers/crypto/hisilicon/qm.o: In function `hisi_qm_uninit':
(.text+0x2918): undefined reference to `uacce_remove'
make[1]: *** [vmlinux] Error 1
make: *** [autoksyms_recursive] Error 2

This patch fixes the config dependency for QM and ZIP.

reported-by: Hulk Robot &lt;hulkci@huawei.com&gt;
Suggested-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Signed-off-by: Hongbo Yao &lt;yaohongbo@huawei.com&gt;
Signed-off-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - Add aead support on SEC2</title>
<updated>2020-01-16T07:18:15Z</updated>
<author>
<name>Zaibo Xu</name>
<email>xuzaibo@huawei.com</email>
</author>
<published>2020-01-11T02:41:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2f072d75d1ab32e9c7c43a54398f4360a0a42d5e'/>
<id>urn:sha1:2f072d75d1ab32e9c7c43a54398f4360a0a42d5e</id>
<content type='text'>
authenc(hmac(sha1),cbc(aes)), authenc(hmac(sha256),cbc(aes)), and
authenc(hmac(sha512),cbc(aes)) support are added for SEC v2.

Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - select CRYPTO_SKCIPHER, not CRYPTO_BLKCIPHER</title>
<updated>2019-12-11T08:36:55Z</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2019-11-29T18:15:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8e8c778d9ed4fdc5a9af108c7023bfb640a673f2'/>
<id>urn:sha1:8e8c778d9ed4fdc5a9af108c7023bfb640a673f2</id>
<content type='text'>
Another instance of CRYPTO_BLKCIPHER made it in just after it was
renamed to CRYPTO_SKCIPHER.  Fix it.

Fixes: 416d82204df4 ("crypto: hisilicon - add HiSilicon SEC V2 driver")
Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - Use the offset fields in sqe to avoid need to split scatterlists</title>
<updated>2019-12-11T08:34:45Z</updated>
<author>
<name>Jonathan Cameron</name>
<email>Jonathan.Cameron@huawei.com</email>
</author>
<published>2019-11-19T05:42:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=484a897ffa3005f16cd9a31efd747bcf8155826f'/>
<id>urn:sha1:484a897ffa3005f16cd9a31efd747bcf8155826f</id>
<content type='text'>
We can configure sgl offset fields in ZIP sqe to let ZIP engine read/write
sgl data with skipped data. Hence no need to splite the sgl.

Fixes: 62c455ca853e (crypto: hisilicon - add HiSilicon ZIP accelerator support)
Signed-off-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Signed-off-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - add HiSilicon SEC V2 driver</title>
<updated>2019-11-22T10:48:36Z</updated>
<author>
<name>Zaibo Xu</name>
<email>xuzaibo@huawei.com</email>
</author>
<published>2019-11-13T11:11:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=416d82204df44ef727de6eafafeaa4d12fdc78dc'/>
<id>urn:sha1:416d82204df44ef727de6eafafeaa4d12fdc78dc</id>
<content type='text'>
SEC driver provides PCIe hardware device initiation with
AES, SM4, and 3DES skcipher algorithms registered to Crypto.
It uses Hisilicon QM as interface to CPU.

Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - use sgl API to get sgl dma addr and len</title>
<updated>2019-11-01T05:42:47Z</updated>
<author>
<name>Zhou Wang</name>
<email>wangzhou1@hisilicon.com</email>
</author>
<published>2019-10-26T02:57:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f0c8b6a1e1454f1645463e8ffb3e027fc597867c'/>
<id>urn:sha1:f0c8b6a1e1454f1645463e8ffb3e027fc597867c</id>
<content type='text'>
Use sgl API to get sgl dma addr and len, this will help to avoid compile
error in some platforms. So NEED_SG_DMA_LENGTH can be removed here, which
can only be selected by arch code.

Signed-off-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Suggested-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Acked-by: Ard Biesheuvel &lt;ard.biesheuvel@linaro.org&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: skcipher - rename the crypto_blkcipher module and kconfig option</title>
<updated>2019-11-01T05:42:47Z</updated>
<author>
<name>Eric Biggers</name>
<email>ebiggers@google.com</email>
</author>
<published>2019-10-25T19:41:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b95bba5d01141ba919c99ea6fde206727f3b3eb4'/>
<id>urn:sha1:b95bba5d01141ba919c99ea6fde206727f3b3eb4</id>
<content type='text'>
Now that the blkcipher algorithm type has been removed in favor of
skcipher, rename the crypto_blkcipher kernel module to crypto_skcipher,
and rename the config options accordingly:

	CONFIG_CRYPTO_BLKCIPHER =&gt; CONFIG_CRYPTO_SKCIPHER
	CONFIG_CRYPTO_BLKCIPHER2 =&gt; CONFIG_CRYPTO_SKCIPHER2

Signed-off-by: Eric Biggers &lt;ebiggers@google.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - select NEED_SG_DMA_LENGTH in qm Kconfig</title>
<updated>2019-10-23T08:46:56Z</updated>
<author>
<name>Zhou Wang</name>
<email>wangzhou1@hisilicon.com</email>
</author>
<published>2019-10-11T11:18:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b981744ef04f7e8cb6931edab50021fff3c8077e'/>
<id>urn:sha1:b981744ef04f7e8cb6931edab50021fff3c8077e</id>
<content type='text'>
To avoid compile error in some platforms, select NEED_SG_DMA_LENGTH in
qm Kconfig.

Fixes: dfed0098ab91 ("crypto: hisilicon - add hardware SGL support")
Signed-off-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Reported-by: kbuild test robot &lt;lkp@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - add HiSilicon HPRE accelerator</title>
<updated>2019-10-10T12:36:31Z</updated>
<author>
<name>Zaibo Xu</name>
<email>xuzaibo@huawei.com</email>
</author>
<published>2019-09-30T09:20:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c8b4b477079d1995cc0a1c10d5cdfd02be938cdf'/>
<id>urn:sha1:c8b4b477079d1995cc0a1c10d5cdfd02be938cdf</id>
<content type='text'>
The HiSilicon HPRE accelerator implements RSA and DH algorithms. It
uses Hisilicon QM as interface to CPU.

This patch provides PCIe driver to the accelerator and registers its
algorithms to crypto akcipher and kpp interfaces.

Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Hui Tang &lt;tanghui20@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
