<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/crypto/hisilicon, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/crypto/hisilicon?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/crypto/hisilicon?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-03T04:37:26Z</updated>
<entry>
<title>crypto: hisilicon - Fix build error</title>
<updated>2020-04-03T04:37:26Z</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2020-03-30T08:36:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b5f13031cd8da1b8f1e277d03a773dc46f7cff11'/>
<id>urn:sha1:b5f13031cd8da1b8f1e277d03a773dc46f7cff11</id>
<content type='text'>
When UACCE is m, CRYPTO_DEV_HISI_QM cannot be built-in.
But CRYPTO_DEV_HISI_QM is selected by CRYPTO_DEV_HISI_SEC2
and CRYPTO_DEV_HISI_HPRE unconditionally, which may leads this:

drivers/crypto/hisilicon/qm.o: In function 'qm_alloc_uacce':
drivers/crypto/hisilicon/qm.c:1579: undefined reference to 'uacce_alloc'

Add Kconfig dependency to enforce usable configurations.

Fixes: 47c16b449921 ("crypto: hisilicon - qm depends on UACCE")
Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec2 - Add new create qp process</title>
<updated>2020-03-20T03:36:50Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2020-03-10T08:42:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0b5e43bc1258bb400378fed99beae032dbece045'/>
<id>urn:sha1:0b5e43bc1258bb400378fed99beae032dbece045</id>
<content type='text'>
Combine found device and created qp into one operation instead of found
device and create qp both are independent operations. when execute
multiple tasks, the different threads may find same device at the same
time, but the number of queues is insufficient on the device. causing
one of threads fail to create a qp. Now fix this, First find device then
create qp, if result failure. the current thread will find next device.

Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Shukun Tan &lt;tanshukun1@huawei.com&gt;
Reviewed-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Reviewed-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/hpre - Optimize finding hpre device process</title>
<updated>2020-03-20T03:36:50Z</updated>
<author>
<name>Hui Tang</name>
<email>tanghui20@huawei.com</email>
</author>
<published>2020-03-10T08:42:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0f4146fadc580b7b479aa46a9991ed451ed911eb'/>
<id>urn:sha1:0f4146fadc580b7b479aa46a9991ed451ed911eb</id>
<content type='text'>
Optimize finding hpre device process according to priority of numa
distance.

Signed-off-by: Hui Tang &lt;tanghui20@huawei.com&gt;
Signed-off-by: Shukun Tan &lt;tanshukun1@huawei.com&gt;
Reviewed-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Reviewed-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/zip - Use hisi_qm_alloc_qps_node() when init ctx</title>
<updated>2020-03-20T03:36:50Z</updated>
<author>
<name>Shukun Tan</name>
<email>tanshukun1@huawei.com</email>
</author>
<published>2020-03-10T08:42:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=18f1ab3f74d61f773dcad257783bfbcef9ac10ea'/>
<id>urn:sha1:18f1ab3f74d61f773dcad257783bfbcef9ac10ea</id>
<content type='text'>
Encapsulate hisi_qm_alloc_qps_node() to new interface to replace
find_zip_device(), which will fix the bug of creating QP failure
especially in multi-thread scenario.

Signed-off-by: Shukun Tan &lt;tanshukun1@huawei.com&gt;
Reviewed-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Reviewed-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - Put device finding logic into QM</title>
<updated>2020-03-20T03:36:50Z</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2020-03-10T08:42:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3f1ec97aacf19eb44162fc9c413eb4cd66f62002'/>
<id>urn:sha1:3f1ec97aacf19eb44162fc9c413eb4cd66f62002</id>
<content type='text'>
Use struct hisi_qm to maintain device list. Meanwhile, add two external
interface into qm, merge find proper device and create qp into QP alloc
logic, merge release qps into QP free logic.

Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Shukun Tan &lt;tanshukun1@huawei.com&gt;
Reviewed-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Reviewed-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec2 - Add pbuffer mode for SEC driver</title>
<updated>2020-03-12T12:00:14Z</updated>
<author>
<name>Longfang Liu</name>
<email>liulongfang@huawei.com</email>
</author>
<published>2020-03-05T02:06:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=74b58db8b7edfadff4a1ed2eb195ab45570a33a9'/>
<id>urn:sha1:74b58db8b7edfadff4a1ed2eb195ab45570a33a9</id>
<content type='text'>
In the scenario of SMMU translation, the SEC performance of short messages
(&lt;512Bytes) cannot meet our expectations. To avoid this, we reserve the
plat buffer (PBUF) memory for small packets when creating TFM.

Signed-off-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec2 - Update IV and MAC operation</title>
<updated>2020-03-12T12:00:14Z</updated>
<author>
<name>Longfang Liu</name>
<email>liulongfang@huawei.com</email>
</author>
<published>2020-03-05T02:06:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2514f5595db7287b0708a21ee40a3278dade69dc'/>
<id>urn:sha1:2514f5595db7287b0708a21ee40a3278dade69dc</id>
<content type='text'>
We have updated the operation method of IV and MAC address
to prepare for pbuf patch and fixed coding style.

Signed-off-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec2 - Add iommu status check</title>
<updated>2020-03-12T12:00:14Z</updated>
<author>
<name>Longfang Liu</name>
<email>liulongfang@huawei.com</email>
</author>
<published>2020-03-05T02:06:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8824bc5ed1e7fbc23529c9b2e799bb9414cb6e52'/>
<id>urn:sha1:8824bc5ed1e7fbc23529c9b2e799bb9414cb6e52</id>
<content type='text'>
In order to improve performance of small packets (&lt;512Bytes)
in SMMU translation scenario, we need to identify the type of IOMMU
in the SEC probe to process small packets by a different method.

Signed-off-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec2 - Add workqueue for SEC driver.</title>
<updated>2020-03-12T12:00:14Z</updated>
<author>
<name>Ye Kai</name>
<email>yekai13@huawei.com</email>
</author>
<published>2020-03-05T02:06:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a13c97118749954a9f47a3b5fc47457baf664f2d'/>
<id>urn:sha1:a13c97118749954a9f47a3b5fc47457baf664f2d</id>
<content type='text'>
Allocate one workqueue for each QM instead of one for all QMs,
we found the throughput of SEC engine can be increased to
the hardware limit throughput during testing sec2 performance.
so we added this scheme.

Signed-off-by: Ye Kai &lt;yekai13@huawei.com&gt;
Signed-off-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - Use one workqueue per qm instead of per qp</title>
<updated>2020-03-12T12:00:14Z</updated>
<author>
<name>Shukun Tan</name>
<email>tanshukun1@huawei.com</email>
</author>
<published>2020-03-05T02:06:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=57ca81245f4db4a0222d545f8f5d4709544c26cf'/>
<id>urn:sha1:57ca81245f4db4a0222d545f8f5d4709544c26cf</id>
<content type='text'>
Since SEC need not so many workqueues as our test, we just use
one workqueue created by the device driver of QM if necessary,
which will also reduce CPU waste without any throughput decreasing.

Signed-off-by: Shukun Tan &lt;tanshukun1@huawei.com&gt;
Signed-off-by: Zaibo Xu &lt;xuzaibo@huawei.com&gt;
Reviewed-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
