wireguard-linux/drivers/dma/xilinx, branch jd/unified-crypt-queue

dmaengine: xilinx_dma: In dma channel probe fix node order dependency

2020-02-25T05:47:54Z

In overlay application we noticed that dma channel node probe order is inverted i.e s2mm channel is probed first followed by mm2s channel. The reason for this inversion is fdtoverlay utility which uses a function called fdt_add_subnode(*). It stores the subnodes after the properties, this has the effect of inserting the new subnode before any others and the end result is a reversal. Because of this inverted channel probe order, the node probed first is assigned a '0' index instead of Channel ID should be '0' for tx and '1' for rx and dmatest client using the DT convention fails in dma transfer as channel are swapped. To fix above behavior and make channel assignment index independent of probe order, always assign mm2s channel at '0' index and the s2mm channel at IP specific fixed offset derived from the max_channels count. Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1580388865-9960-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Extend dma_config structure to store max channel count

2020-02-25T05:47:53Z

Extend dma_config structure to store the max channel count. This input is used to populate dma device channel nodes at the fixed offset. It serves as a preparatory patch for removing dma channel DT node order dependency, added in the subsequent commit. Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1580388865-9960-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all

2020-02-24T16:53:48Z

Reset DMA channel after stop to ensure that pending transfers and FIFOs in the datapath are flushed or completed. It also cleanup the terminate path and removes stop for the cyclic mode as after the reset stop is not required. This fixes intermittent data verification failure when xilinx dma test the client is stressed and loaded/unloaded multiple times. Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1580283909-32678-1-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: zynqmp_dma: fix burst length configuration

2020-01-21T09:19:30Z

Since the dma engine expects the burst length register content as power of 2 value, the burst length needs to be converted first. Additionally add a burst length range check to avoid corrupting unrelated register bits. Signed-off-by: Matthias Fend Link: https://lore.kernel.org/r/20200115102249.24398-1-matthias.fend@wolfvision.net Signed-off-by: Vinod Koul

Merge branch 'fixes' into next

2019-11-14T10:32:51Z

dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support

2019-11-06T17:08:02Z

Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Extend dma_config struct to store irq routine handle

2019-11-06T17:08:01Z

Extend dma_config structure to store irq routine handle. It enables runtime handler selection based on xdma_ip_type and serves as preparatory patch for adding MCDMA IP support. Signed-off-by: Radhey Shyam Pandey Suggested-by: Vinod Koul Link: https://lore.kernel.org/r/1571763622-29281-6-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Remove axidma multichannel mode support

2019-11-06T17:08:01Z

The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver. So inline with it remove axidma multichannel support from from the driver. Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1571763622-29281-5-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Clear desc_pendingcount in xilinx_dma_reset

2019-10-20T14:05:27Z

Whenever we reset the channel, we need to clear desc_pendingcount along with desc_submitcount. Otherwise when a new transaction is submitted, the irq coalesce level could be programmed to an incorrect value in the axidma case. This behavior can be observed when terminating pending transactions with xilinx_dma_terminate_all() and then submitting new transactions without releasing and requesting the channel. Signed-off-by: Nicholas Graumann Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1571150904-3988-8-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul

dmaengine: xilinx_dma: Print debug message when no free tx segments

2019-10-20T14:05:27Z

The driver should not run out of tx segments in normal operation. But, if the user attempts to prepare a transaction with a large sg list, the driver may not have enough free segments to accommodate the request. Log a message at the debug level to inform the user in case they are experiencing issues. Signed-off-by: Nicholas Graumann Signed-off-by: Radhey Shyam Pandey Link: https://lore.kernel.org/r/1571150904-3988-7-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul