<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/amd/display/amdgpu_dm, branch jd/shorter-socket-lock</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/display/amdgpu_dm?h=jd%2Fshorter-socket-lock</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/display/amdgpu_dm?h=jd%2Fshorter-socket-lock'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-17T21:31:38Z</updated>
<entry>
<title>drm/amdgpu/display: give aux i2c buses more meaningful names</title>
<updated>2020-04-17T21:31:38Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-04-16T18:44:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7daec99fdcde7b01595134a3d8f385bc1009f1d8'/>
<id>urn:sha1:7daec99fdcde7b01595134a3d8f385bc1009f1d8</id>
<content type='text'>
Mirror what we do for i2c display buses.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fix aux registration (v2)</title>
<updated>2020-04-17T21:31:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-04-16T18:20:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=00a8037e2070890b43ceeda326b8192323b5fa59'/>
<id>urn:sha1:00a8037e2070890b43ceeda326b8192323b5fa59</id>
<content type='text'>
We were registering the aux device in the MST late_register
rather than the regular one.

v2: handle eDP as well

Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration (v4)")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fix warning when compiling without debugfs</title>
<updated>2020-04-08T21:53:11Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-04-08T13:30:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7e7ea24f0b46cd3078bc9af29d1c1aced89d1c8e'/>
<id>urn:sha1:7e7ea24f0b46cd3078bc9af29d1c1aced89d1c8e</id>
<content type='text'>
fixes unused variable warning.

Reported-by: Eric Biggers &lt;ebiggers@kernel.org&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Make cursor source translation adjustment optional</title>
<updated>2020-04-07T18:20:45Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-04-05T20:41:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d243b6ffde7a3717c38b31dbc9c8c562f066d6ef'/>
<id>urn:sha1:d243b6ffde7a3717c38b31dbc9c8c562f066d6ef</id>
<content type='text'>
[Why]
In some usecases, like tiled display, the stream and plane configuration
can be setup in a way where the caller expects DAL to perform the
clipping, eg:

P0:
src_rect(0, 0, w, h)
dst_rect(0, 0, w, h)

P1:
src_rect(w, 0, w, h)
dst_rect(0, 0, w, h)

Cursor is enabled on both streams with the same position.

This can result in double cursor on tiled display, even though this
behavior is technically correct from the DC interface point of view.

We need a mechanism to control this dynamically.

[How]
This is something that should live in the DM layer based on detection
of the specified configuration but it's not something that we really
have enough information to deal with today.

Add a flag to the cursor position state that specifies whether we
want DC to do the translation or not and make it opt-in and let
the DM decide when to do it.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix incorrect cursor pos on scaled primary plane</title>
<updated>2020-04-07T18:20:45Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-04-05T20:40:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=56b922c106cd13e00b4cd58dfc4037bc21daf51a'/>
<id>urn:sha1:56b922c106cd13e00b4cd58dfc4037bc21daf51a</id>
<content type='text'>
[Why]
Cursor pos is correctly adjusted from DC side for source rect offset
on DCN ASIC, but only on the overlay.

This is because DM places offsets the cursor for primary planes only
to workaround missing code in DCE for the adjustment we're now correctly
doing in DC for DCN ASIC.

[How]
Drop the adjustment for source rect from the DM side of things and put
the code where it actually belongs - in DC on the pipe level.

This matches what we do for DCN now.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Zhan Liu &lt;Zhan.Liu@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Avoid create MST prop after registration</title>
<updated>2020-04-07T18:10:24Z</updated>
<author>
<name>Jerry (Fangzhi) Zuo</name>
<email>Jerry.Zuo@amd.com</email>
</author>
<published>2020-04-05T20:41:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8c61b31e3c3f7dd843ebbf1cc02ca352b66f123f'/>
<id>urn:sha1:8c61b31e3c3f7dd843ebbf1cc02ca352b66f123f</id>
<content type='text'>
[Why]
Prop are created at boot stage, and not allowed to create new prop
after device registration.

[How]
Reuse the connector property from SST if exist.

Signed-off-by: Jerry (Fangzhi) Zuo &lt;Jerry.Zuo@amd.com&gt;
Reviewed-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: increase HDCP authentication delay</title>
<updated>2020-03-31T16:44:29Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2020-03-30T17:43:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d6e7042f4e80f2f139c23237da63ffcb060b0710'/>
<id>urn:sha1:d6e7042f4e80f2f139c23237da63ffcb060b0710</id>
<content type='text'>
[Why]
Some displays have an issue where the hdcp chips are initialized after the
display has already lit up. This means we can sometimes authentication too early
and cause authentication failures.

This happens when HDCP is enabled and the display is power cycled. Normally we
will authenticate 2 seconds after the display is lit, but some displays need a
bit more time.

[How]
Increase delay to 3 second before we start authentication.

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Correctly cancel future watchdog and callback events</title>
<updated>2020-03-31T16:44:29Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2020-03-30T17:37:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2ebbe7c9d11d7fea296c4997b80d2590a0928424'/>
<id>urn:sha1:2ebbe7c9d11d7fea296c4997b80d2590a0928424</id>
<content type='text'>
[Why]
-We need to cancel future callbacks/watchdogs events when a callback/watchdog event happens

[How]
-fix typo in event_callback()
	-cancel callback, not watchdog
-cancel watchdog events in event_watchdog_timer().

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Don't try hdcp1.4 when content_type is set to type1</title>
<updated>2020-03-31T16:44:29Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2020-03-30T17:29:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=c2850c125d919efbb3a9ab46410d23912934f585'/>
<id>urn:sha1:c2850c125d919efbb3a9ab46410d23912934f585</id>
<content type='text'>
[Why]
When content type property is set to 1. We should enable hdcp2.2 and if we cant
then stop. Currently the way it works in DC is that if we fail hdcp2, we will
try hdcp1 after.

[How]
Use link config to force disable hdcp1.4 when type1 is set.

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable BT2020 in COLOR_ENCODING property</title>
<updated>2020-03-31T16:26:15Z</updated>
<author>
<name>Stylon Wang</name>
<email>stylon.wang@amd.com</email>
</author>
<published>2020-03-13T14:21:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=00755bb79cb239905780965c9bc128de7073a9f0'/>
<id>urn:sha1:00755bb79cb239905780965c9bc128de7073a9f0</id>
<content type='text'>
[Why]
BT2020 is not supported in COLOR_ENCODING property of planes.  Only
BT601 and BT709 was available.

[How]
Allow BT2020 as legit value in setting COLOR_ENCODING property.

Signed-off-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
