<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/amd/display/amdgpu_dm, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/display/amdgpu_dm?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/display/amdgpu_dm?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-08-12T13:45:03Z</updated>
<entry>
<title>drm/amd/display: make DC_RUN_WITH_PREEMPTION_ENABLED misuse a build error</title>
<updated>2026-08-12T13:45:03Z</updated>
<author>
<name>Mikhail Gavrilov</name>
<email>mikhail.v.gavrilov@gmail.com</email>
</author>
<published>2026-07-30T06:53:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0d710af8e4abdd1fa500bddbab7c0ee47fc98143'/>
<id>urn:sha1:0d710af8e4abdd1fa500bddbab7c0ee47fc98143</id>
<content type='text'>
Inside an FPU compilation unit DC_FP_START() and DC_FP_END() are defined
as BUILD_BUG(), so using them there fails the build.  That was done on
purpose by
commit a574f53ed52e ("drm/amd/display: Permit DC_FP_START/END only in non-FP compilation units").

DC_RUN_WITH_PREEMPTION_ENABLED() was added later by
commit 3539437f354b ("drm/amd/display: Move FPU Guards From DML To DC - Part 1")
and defined as a plain pass-through in that same branch instead.  A wrap
placed inside an FPU compilation unit therefore compiles cleanly, reads
as correct during review, and does nothing at all.

This is not hypothetical.  While chasing a "scheduling while atomic"
splat in dc_create_plane_state() on PREEMPT_RT, an attempt to place the
guard further up the call chain, in dml21_add_phantom_plane() in
dc/dml2_0/dml21/dml21_utils.c, had no effect for exactly this reason:
dc/dml2_0/Makefile applies CC_FLAGS_FPU to every object under that
directory, and the top level Makefile adds -D_LINUX_FPU_COMPILATION_UNIT
to CC_FLAGS_FPU.

Define the macro as BUILD_BUG() there as well, so that the mistake is a
compile error rather than a guard that silently does nothing.  The code
argument is kept in the expansion so the BUILD_BUG() failure is not
accompanied by set-but-unused diagnostics for variables assigned inside
it.

No current user is affected.  dc/core/dc_stream.c and
dc/resource/dcn32/dcn32_resource.c are outside the dml directories, and
dc/dml2_0/dml2_wrapper.c and dc/dml2_0/dml21/dml21_wrapper.c are built
without the FPU flags because dc/dml2_0/Makefile replaces their CFLAGS
with CC_FLAGS_NO_FPU and removes CC_FLAGS_FPU.

Link: https://lore.kernel.org/all/1ead313022bc62dce1f42af9f855727eb9074443.camel@web.de/
Signed-off-by: Mikhail Gavrilov &lt;mikhail.v.gavrilov@gmail.com&gt;
Reviewed-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix NULL pointer dereference in amdgpu_dm_crtc_set_vblank()</title>
<updated>2026-08-12T13:38:11Z</updated>
<author>
<name>Samuel Pitoiset</name>
<email>samuel.pitoiset@gmail.com</email>
</author>
<published>2026-08-07T14:58:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7b1b31bf6942e6f43509b48da23f8e27269aac39'/>
<id>urn:sha1:7b1b31bf6942e6f43509b48da23f8e27269aac39</id>
<content type='text'>
amdgpu_dm_crtc_set_vblank() dereferences acrtc_state-&gt;stream when
vblank is enabled/queried from DRM_IOCTL_MODE_CRTC_GET_SEQUENCE before
a stream is attached to it.

BUG: kernel NULL pointer dereference, address: 0000000000000008
RIP: amdgpu_dm_crtc_set_vblank+0x6b/0x4d0 [amdgpu]
Call Trace:
 drm_vblank_enable
 drm_vblank_get
 drm_crtc_get_sequence_ioctl
 drm_ioctl_kernel
 drm_ioctl

Reproduced by running VKCTS with WSI tests enabled on RADV.

Guard the enable path on acrtc_state-&gt;stream being non-NULL, matching
the existing checks in this function.

Fixes: 34d66bc7ff10 ("drm/amd/display: Fix Xorg desktop unresponsive on Replay panel")
Reviewed-by: Melissa Wen &lt;mwen@igalia.com&gt;
Signed-off-by: Samuel Pitoiset &lt;samuel.pitoiset@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Set native cursor mode for disabled CRTCs again</title>
<updated>2026-08-06T17:45:44Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2026-08-03T12:45:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9d07a6ea186cefa25dd3cd61cd1261261133e8b2'/>
<id>urn:sha1:9d07a6ea186cefa25dd3cd61cd1261261133e8b2</id>
<content type='text'>
It was regressed by a refactor. Let's fix it again.

Always set native cursor mode when the CRTC is disabled,
to make sure it doesn't cause atomic commits to fail when
they are trying to disable the CRTC.

Fixes: 87a6dab12fc0 ("drm/amd/display: add cursor module")
Cc: Alex Hung &lt;alex.hung@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: allow self-refresh exit while entry is blocked</title>
<updated>2026-08-06T16:48:00Z</updated>
<author>
<name>David Weber</name>
<email>weber.aulendorf@gmail.com</email>
</author>
<published>2026-07-30T03:32:00Z</published>
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<id>urn:sha1:bd0c00982166d34ed47b11ba29cd8bf2950cc2e2</id>
<content type='text'>
amdgpu_dm_crtc_set_static_screen_optimze() maps sso_enable to the
Replay and PSR1 vsync events. allow_sr_entry is an entry gate, but the
helper currently applies it to both directions.

A non-fast update clears allow_sr_entry. During a modeset, a separate
hardware-programming event keeps self-refresh blocked while the stream
is reprogrammed. If vblank is enabled before the entry delay expires,
the ISM calls the helper with sso_enable false. The early return drops
the disable request, so the vsync events are not set.

After enough fast commits, allow_sr_entry becomes true and the
hardware-programming event can be cleared. Since the vblank reference
remains held, there is no further zero-to-one vblank transition to
restore the missing vsync events. Replay or PSR1 can then become active
while vblank is still enabled.

Gate only requests that enable static-screen optimization. Always
process disable requests so a vblank requestor keeps Replay and PSR1
blocked.

On a Phoenix system, repeated SDDM-to-VT handoffs produced stuck flips
followed by flip_done and commit-wait timeouts. The timeout was not
observed with this change applied.

Fixes: 3c108046e1d6 ("drm/amd/display: Add power module on Linux")
Assisted-by: Codex:gpt-5.6-sol
Assisted-by: Claude:opus-5
Signed-off-by: David Weber &lt;weber.aulendorf@gmail.com&gt;
Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Disable DP audio spread spectrum for Cyan Skillfish</title>
<updated>2026-08-06T16:47:56Z</updated>
<author>
<name>Travis K. Bangs</name>
<email>tbangs89@gmail.com</email>
</author>
<published>2026-08-03T19:13:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f3a2d86587432fdd9a6d401507b60a01153453c5'/>
<id>urn:sha1:f3a2d86587432fdd9a6d401507b60a01153453c5</id>
<content type='text'>
The VBIOS for Cyan Skillfish devices (DCN201) indicates there is
DisplayPort ref clock spread spectrum downspread, so the audio clock
is corrected for it.

However, the clock source in this hardware does not seem to actually be
running with a clock downspread, so DisplayPort audio desyncs with video
after several minutes.

Ignore dprefclk SS downspread on CYAN_SKILLFISH2 asic.

Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5429
Signed-off-by: Travis K. Bangs &lt;tbangs89@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix more KUnit connector use-after-free bugs</title>
<updated>2026-08-06T16:44:10Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2026-07-24T19:12:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1cdb23735d508c6f3eb70c86fdf2f70d1d395567'/>
<id>urn:sha1:1cdb23735d508c6f3eb70c86fdf2f70d1d395567</id>
<content type='text'>
drmm_connector_init() and drmm_encoder_init() register their cleanup
(drm_connector_cleanup() / drm_encoder_cleanup()) as DRM-managed actions
tied to the drm_device lifetime. When the object memory is owned by
KUnit, it is freed before that action runs, so the cleanup touches freed
memory. Allocate these objects with drmm_kzalloc() so their lifetime
matches the cleanup action.

Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Assisted-by: Copilot:Claude-Opus-4.8
Acked-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Configure all CRC engines in pipe CRC source path</title>
<updated>2026-08-06T16:44:05Z</updated>
<author>
<name>Wayne Lin</name>
<email>Wayne.Lin@amd.com</email>
</author>
<published>2026-07-27T05:45:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ef45aaf73717738ab123ab0350ff59753cce8ff4'/>
<id>urn:sha1:ef45aaf73717738ab123ab0350ff59753cce8ff4</id>
<content type='text'>
Iterate every CRC engine instance when enabling or disabling the pipe CRC
source so DCN31x OTG_CRC1_EN is handled alongside OTG_CRC_EN, matching the
legacy shared enable behavior used by DisplayCRC multi-ROI.

Reviewed-by: ChiaHsuan (Tom) Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Cover crtc destroy_state stream release</title>
<updated>2026-08-06T16:43:28Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>bhawanpreet.lakha@amd.com</email>
</author>
<published>2026-07-21T19:59:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=79e9adea27598d1787ee3bd727cb94933daea4c3'/>
<id>urn:sha1:79e9adea27598d1787ee3bd727cb94933daea4c3</id>
<content type='text'>
Add dm_test_crtc_destroy_state_releases_stream to cover the cur-&gt;stream
branch of amdgpu_dm_crtc_destroy_state(), complementing the existing
no-stream test.

The test attaches a DC stream to the CRTC state and takes an extra stream
reference so the destroy path drops back to the KUnit-managed reference
instead of freeing the stream, then verifies exactly one reference was
released.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;bhawanpreet.lakha@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Cover crtc vblank restore replay-supported path</title>
<updated>2026-08-06T16:43:24Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>bhawanpreet.lakha@amd.com</email>
</author>
<published>2026-07-21T19:45:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=76388d61df1650bdae43e343feb33538f0cd1c8b'/>
<id>urn:sha1:76388d61df1650bdae43e343feb33538f0cd1c8b</id>
<content type='text'>
Add dm_test_crtc_enable_vblank_ips_restore_replay to cover the
pr-&gt;config.replay_supported side of the sr_supported OR in
amdgpu_dm_crtc_set_vblank().

The existing IPS restore test establishes self-refresh support via the PSR
version. This test instead marks the PSR version unsupported and sets
replay_supported, forcing the sr_supported computation to fall through to
the replay branch while still calling drm_crtc_vblank_restore().

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;bhawanpreet.lakha@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Cover crtc vblank IPS self-refresh restore</title>
<updated>2026-08-06T16:43:14Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>bhawanpreet.lakha@amd.com</email>
</author>
<published>2026-07-21T19:37:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1296ec6a4b3585336eddb6aa6f7bd80120b5db81'/>
<id>urn:sha1:1296ec6a4b3585336eddb6aa6f7bd80120b5db81</id>
<content type='text'>
Add dm_test_crtc_enable_vblank_ips_restore to cover the IPS/self-refresh
branch of amdgpu_dm_crtc_set_vblank() that calls drm_crtc_vblank_restore().

The test primes the DC with ips_support set and IPS not fully disabled, a
supported PSR version (self-refresh supported) and an immediate-disable
vblank config, so all four conditions gating the restore hold. A stub
get_vblank_timestamp hook is installed on the CRTC so the restore helper
passes its sanity check, and the enable path then runs to completion.

Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;bhawanpreet.lakha@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
