wireguard-linux/drivers/gpu/drm/amd/display/dc, branch stable

drm/amd/display: fix BT.2020 YCbCr output CSC matrices for DCE

2026-08-12T13:43:19Z

The commit cited by the Fixes tag added separate limited and full-range BT.2020 YCbCr entries to the DCE output CSC tables, but populated both entries with the same matrix copied from the common DC table. That matrix combined full-range scaling with limited-range luma offset and was incorrect for both limited and full-range output. Replace the coefficients in both entries in the DCE paths with those from the new COLOR_SPACE_YCBCR2020_LIMITED_TYPE and COLOR_SPACE_YCBCR2020_FULL_TYPE entries in the preceding commit ("drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix"). Fixes: 51e6668ab4ba ("drm/amd/display: add missing CSC entries for BT.2020 for DCE IPs") Assisted-by: OpenAI-Codex:GPT-5.6-Sol Tested-by: Igor Paunovic Tested-by: Satyajit Roy Signed-off-by: Nathan Lucas Signed-off-by: Alex Deucher

drm/amd/display: fix BT.2020 YCbCr limited output CSC matrix

2026-08-12T13:42:44Z

COLOR_SPACE_YCBCR2020_TYPE, which is selected for COLOR_SPACE_2020_YCBCR_LIMITED color_space, has coefficients that are incorrect for limited-range output. Its luma and chroma scaling is full-range so output is too bright and colors are incorrect. COLOR_SPACE_YCBCR2020_TYPE is closer to a full-range conversion matrix with incorrect luma offset, so correct the luma offset for full-range and rename it to COLOR_SPACE_YCBCR2020_FULL_TYPE. Add COLOR_SPACE_YCBCR2020_LIMITED_TYPE with correct scaling and range for limited-range output. Fix related functions so COLOR_SPACE_YCBCR2020_LIMITED_TYPE and COLOR_SPACE_YCBCR2020_FULL_TYPE are correctly selected based on dc_color_space. Derivation of both matrices follows ITU-T H.273: Table 4, MatrixCoefficients 9, BT.2020-NCL weights: KR = 0.2627, KB = 0.0593, KG = 1 - KR - KB = 0.6780. Equations 45-47 in matrix form: [ KR KG KB 0 ] M2020_NCL = [ -KR/(2(1-KB)) -KG/(2(1-KB)) 1/2 0 ] [ 1/2 -KG/(2(1-KR)) -KB/(2(1-KR)) 0 ] [ 0 0 0 1 ] Limited and Full transforms based on equations 30-32 and 36-38 with bit depth 10, normalized by 1023: [ 876/1023 0 0 64/1023 ] MLimited = [ 0 896/1023 0 512/1023 ] [ 0 0 896/1023 512/1023 ] [ 0 0 0 1 ] [ 1023/1023 0 0 0 ] MFull = [ 0 1023/1023 0 512/1023 ] [ 0 0 1023/1023 512/1023 ] [ 0 0 0 1 ] M2020_NCL_Limited = MLimited x M2020_NCL M2020_NCL_Full = MFull x M2020_NCL The upper three rows of M2020_NCL_* are stored in CR, Y, CB order. Each M2020_NCL_* value is stored as Round(value * 8192) in its 16-bit two's-complement representation. Fixes: 973a9c810c78 ("drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix") Assisted-by: OpenAI-Codex:GPT-5.6-Sol Tested-by: Igor Paunovic Tested-by: Satyajit Roy Signed-off-by: Nathan Lucas Signed-off-by: Alex Deucher

drm/amd/display: Relax frame size limit for dcn5/6 DML core funcs files

2026-08-12T13:38:51Z

[Why] During compilation with allmodconfig with KASAN, there appears a Werror: dml2_core_dcn5_funcs_mode_programming.c:11:13: error: stack frame size (2400) exceeds limit (2048) in 'dcn5_mode_programming' [-Werror,-Wframe-larger-than] The dcn5/dcn6 dml2_core_*_funcs_mode_{programming,support} files were split out of dml2_core_dcn4_calcs.o, which carries a relaxed -Wframe-larger-than limit via $(frame_warn_flag) (2056 normally, or 4096 for clang + KASAN/KCSAN + COMPILE_TEST). The split-out files were never added to the per-file CFLAGS override list, so they inherited the strict global default of 2048. This is why these files trip the frame size warning under KASAN while the larger dml2_core_dcn4_calcs.o does not. [How] Apply the same $(frame_warn_flag) and CFLAGS_REMOVE handling used for dml2_core_dcn4_calcs.o to the split-out files: - dml2_core_dcn5_funcs_mode_programming.o - dml2_core_dcn5_funcs_mode_support.o - dml2_core_dcn6_funcs_mode_programming.o - dml2_core_dcn6_funcs_mode_support.o Fixes: 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6") Reviewed-by: Dillon Varone Signed-off-by: Ivan Lipski Reported-by: Mark Brown Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/display: Fix crash in hwss_set_output_transfer_func()

2026-08-06T17:46:24Z

The pipe_ctx->plane_res.hubp pointer is NULL on all DCE hardware, which causes a kernel NULL pointer dereference on all Vega and older GPUs. Let's add a simple NULL check. Fixes: 6bfca938471b ("drm/amd/display: Refactor DPP_SET_OUTPUT_TRANSFER_FUNC to drop pipe_ctx") Signed-off-by: Timur Kristóf Cc: Tomasz Siemek Signed-off-by: Alex Deucher

drm/amd/display: Check for tg ops in dce110_set_avmute

2026-08-06T17:43:27Z

Some older DCE timing generators do not implement is_tg_enabled in their ops table. Calling it unconditionally when waiting for AV mute frames causes a NULL pointer dereference on Southern Islands dGPUs when turning the display off over HDMI. Check that tg and the required ops exist before waiting for frames. Fixes: 414da24137ac ("drm/amd/display: Add AV mute wait frames to dce110_set_avmute") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5557 Tested-by: Viktor Jägersküpper Signed-off-by: Ray Wu Signed-off-by: Alex Deucher

drm/amd/display: Promote DC to 3.2.392

2026-08-06T16:44:30Z

This version brings along the following updates: - Add KUnit tests for crtc functions. - Add KUnit tests for crtc functions. - Add support for dynamic FFE levels. - Configure all CRC engines in pipe CRC source path. - Enable DCN6 compilation. - Fix ABM over VABC. - Fix CRC engine 1 enable/disable on DCN3.1.2+. - Fix MCM blend LUT issues. - Fix seamless mode switch not triggering for HDR to SDR transition. - Fix wb_info leak and NULL deref in writeback. - Increase fclk change latency on dcn351. - Refactor stream validation. - Resize MST HDCP per-connector arrays to 32. - Unify force_yuv debugfs into force_yuv_pixel_format. - Update VRR info packet to support 12-bit refresh rates. Signed-off-by: Taimur Hassan Signed-off-by: Roman Li Reviewed-by: Alex Hung Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Migrate color manager HW and fix MCM blend LUT issues

2026-08-06T16:44:26Z

Combine two related color manager improvements: 1. Migrate MCM/RMCM, shaper and 3DLUT HW programming to dc_plane_cm - Continue convergence with upstream Color Manager refactor - Migrate MCM/RMCM, shaper and 3DLUT programming for dcn401+ to dc_plane_cm - Unify MCM programming across both legacy and 3DLUT DMA paths - Add 3DLUT DMA broadcast support for multi-pipe planes 2. Reprogram MCM blend LUT on blend_enable falling edge - Fix issue where SDR desktop remained desaturated after video playback - Detect blend_enable falling edge (1->0) in surface update detection - Force MCM LUT reprogramming on blend state change Reviewed-by: Dillon Varone Signed-off-by: Rafal Ostrowski Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add FFE level defaults

2026-08-06T16:44:23Z

[How & Why] Follow-up change to set defaults for HDMI FRL training Reviewed-by: Nicholas Kazlauskas Signed-off-by: Relja Vojvodic Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: switch max FFE level cap based on FRL link rate

2026-08-06T16:44:20Z

[How & Why] - Add support for dynamic FFE levels based on debug config and link rate Reviewed-by: Nicholas Kazlauskas Signed-off-by: Relja Vojvodic Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Update BW bounding box unconditionally for DCN6

2026-08-06T16:44:16Z

[Description] DCN6 needs to update BW bounding box in hw init in order to propagate the Alt-Ch aperture info into DML. In this case update unconditionally on dcn6 HW init. Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Roman Li Tested-by: Dan Wheeler Signed-off-by: Alex Deucher