<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/amd/display/dmub, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/display/dmub?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/display/dmub?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-08-06T16:43:44Z</updated>
<entry>
<title>drm/amd/display: Add missing DMUB CACP and PR definitions</title>
<updated>2026-08-06T16:43:44Z</updated>
<author>
<name>Taimur Hassan</name>
<email>Syed.Hassan@amd.com</email>
</author>
<published>2026-07-27T04:11:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f82cee9dd809aca205664d235f7c02c615ad1408'/>
<id>urn:sha1:f82cee9dd809aca205664d235f7c02c615ad1408</id>
<content type='text'>
[Why]
Should have been picked up in 0.1.69.0 promotion commit.

[How]
Add the missing DMUB command-header definitions in dmub_cmd.h:

1. DMUB_CMD__CACP_GET_ACE_CURVE_AREA command ID.
2. Request/response data and command structs.
3. PR runtime flag bit.

Signed-off-by: Taimur Hassan &lt;Syed.Hassan@amd.com&gt;
Signed-off-by: Roman Li &lt;roman.li@amd.com&gt;
Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable DCN6 sources compilation</title>
<updated>2026-08-06T13:53:32Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2026-07-21T13:59:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=992694ad28584188725751f695a85661e8e3797a'/>
<id>urn:sha1:992694ad28584188725751f695a85661e8e3797a</id>
<content type='text'>
- Add hooks in various entry points to perform hw/sw init for DCN6 asic
- Add dependent changes needed to enable DCN6 asic
- Update the Makefiles so that DCN6 related newly added sources are compiled

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add new sources for DCN6</title>
<updated>2026-08-06T13:48:29Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2026-07-22T18:45:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7f7d7ea1fa515157162d0d21245925551ed103a1'/>
<id>urn:sha1:7f7d7ea1fa515157162d0d21245925551ed103a1</id>
<content type='text'>
Add DCN6 code to DC, DML2, and DMUB

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Roman Li &lt;Roman.Li@amd.com&gt;
Reviewed-by: Ivan Lipski &lt;ivan.lipski@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Generalize DMUB memory flushes from host</title>
<updated>2026-07-14T23:12:34Z</updated>
<author>
<name>Dillon Varone</name>
<email>Dillon.Varone@amd.com</email>
</author>
<published>2026-06-23T19:42:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5b69770e945caa1bef6c4848bb279ec09d3e9d4f'/>
<id>urn:sha1:5b69770e945caa1bef6c4848bb279ec09d3e9d4f</id>
<content type='text'>
[WHY&amp;HOW]
Add DMUB service context to aid in platform abstraction when
flushing memory from the host.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Dillon Varone &lt;Dillon.Varone@amd.com&gt;
Signed-off-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: [FW Promotion] Release 0.1.64.0</title>
<updated>2026-07-01T15:17:58Z</updated>
<author>
<name>Taimur Hassan</name>
<email>Syed.Hassan@amd.com</email>
</author>
<published>2026-06-12T22:44:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a91135995ccd6358d0f6ad203d92aaaeaf16a53f'/>
<id>urn:sha1:a91135995ccd6358d0f6ad203d92aaaeaf16a53f</id>
<content type='text'>
Added panel polarity feature

Signed-off-by: Taimur Hassan &lt;Syed.Hassan@amd.com&gt;
Signed-off-by: George Zhang &lt;george.zhang@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Acked-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: [FW Promotion] Release 0.1.63.0</title>
<updated>2026-06-17T20:18:26Z</updated>
<author>
<name>Taimur Hassan</name>
<email>Syed.Hassan@amd.com</email>
</author>
<published>2026-06-05T21:09:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9a591ae691b50b73b106ef78b0c2c56f90fec439'/>
<id>urn:sha1:9a591ae691b50b73b106ef78b0c2c56f90fec439</id>
<content type='text'>
[Why &amp; How]
Add some CACP command and remove some unused struct and enum.

Signed-off-by: Taimur Hassan &lt;Syed.Hassan@amd.com&gt;
Signed-off-by: Chenyu Chen &lt;chen-yu.chen@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support for FRL to DC core</title>
<updated>2026-06-03T17:44:46Z</updated>
<author>
<name>Harry Wentland</name>
<email>harry.wentland@amd.com</email>
</author>
<published>2026-04-24T18:23:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=fdaf63d9a83aeff2f165b45e7073767bbe62f2fc'/>
<id>urn:sha1:fdaf63d9a83aeff2f165b45e7073767bbe62f2fc</id>
<content type='text'>
Here we add support for reading BIOS caps and tie FRL bits
into the rest of DC core.

Signed-off-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reviewed-by: Fangzhi Zuo &lt;Jerry.Zuo@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>ddrm/amd/display: [FW Promotion] Release 0.1.61.0</title>
<updated>2026-06-03T17:44:15Z</updated>
<author>
<name>Taimur Hassan</name>
<email>Syed.Hassan@amd.com</email>
</author>
<published>2026-05-22T09:57:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e81a4c508e690bdb88410dfe51fe71a365f900c1'/>
<id>urn:sha1:e81a4c508e690bdb88410dfe51fe71a365f900c1</id>
<content type='text'>
[Why &amp; How]
Update DMUB related command structure.

Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Taimur Hassan &lt;Syed.Hassan@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN42B DMUB support</title>
<updated>2026-06-03T17:44:05Z</updated>
<author>
<name>Matthew Stewart</name>
<email>Matthew.Stewart2@amd.com</email>
</author>
<published>2026-05-19T01:49:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=827d94e61320ed350705fc1024059f0e74bcc214'/>
<id>urn:sha1:827d94e61320ed350705fc1024059f0e74bcc214</id>
<content type='text'>
[Why &amp; How]
Add DMUB support for DCN42B

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Matthew Stewart &lt;matthew.stewart2@amd.com&gt;
Signed-off-by: Ray Wu &lt;ray.wu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amd/display: dmub_cmd.h: add missing kernel-doc for enums"</title>
<updated>2026-05-18T22:21:07Z</updated>
<author>
<name>James Lin</name>
<email>PingLei.Lin@amd.com</email>
</author>
<published>2026-05-05T22:49:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=67fb68996cb517bda9c2f27f8a33872ecbef5b25'/>
<id>urn:sha1:67fb68996cb517bda9c2f27f8a33872ecbef5b25</id>
<content type='text'>
[Why &amp; How]
This reverts commit f71d0b68ec58b781f4f44ea642846bedce075e85.

1. Auto-generated Header: The file 'dmub_cmd.h' is an auto-generated header
   managed in an external repository (dmu_stg). Manual changes made directly in
   this repository will be overwritten and lost during the next automated weekly
   synchronization.

2. Tooling Compatibility: This header is governed by internal AMD firmware
   standards which require Doxygen formatting for cross-team documentation.
   Moving to kernel-doc syntax may break internal documentation pipelines.

3. Suppressing Warnings: Current 'make htmldocs' and 'make W=1' builds
   do not actively scan 'dmub_cmd.h' for kernel-doc compliance, thus no warnings
   are triggered during standard compilation. To address warnings generated when
   manually running './scripts/kernel-doc', we have added a notice at the file
   header indicating that this is an auto-generated file that does not strictly
   follow kernel-doc formatting. This ensures that any future linting tools or
   manual checks recognize the formatting as intentional.

Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: James Lin &lt;pinglei.lin@amd.com&gt;
Tested-by: Dan Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
