wireguard-linux/drivers/gpu/drm/amd/include/asic_reg, branch stable

drm/amdgpu/gfx6: Add IP block soft reset implementation

2026-08-06T16:47:46Z

Update the register definition for GRBM_SOFT_RESET to match what was in the old radeon driver and use these bits in the soft reset implementation. For the soft reset, use basically the same implementation as GFX7-8, the main difference being the GRBM_SOFT_RESET bit fields and the fact that GFX6 doesn't have MQD/HQD. Reset every block using the GRBM, then proceed to reset the GRBM and SEM blocks using the SRBM. The soft reset also calls the clock and powergating functions of the IP block. This is necessary for correct operation, otherwise the GPU might fall off the PCIe bus. Add a gfx_v6_0_late_init() function for consistency with other GPU generations. This function will later serve the same purpose as it does on GFX7+ when we get around to enable more IRQs on GFX6. Signed-off-by: Timur Kristóf Signed-off-by: Alex Deucher

drm/amd: Add DCN6 register headers

2026-08-06T13:46:28Z

Add new headers for: - dcn 6.0.0 - dpcs 6.0.0 - mmhub 5.0.1 Signed-off-by: Aurabindo Pillai Signed-off-by: Roman Li Reviewed-by: Ivan Lipski Tested-by: Dan Wheeler Signed-off-by: Alex Deucher

drm/amdkfd: add sdma queue counter for gfxv9.4.3

2026-06-17T20:14:11Z

since gfx 9.4.3 HW is calculating accumulated activity counter per-queue in register sdmax_rlcx_utilization_hi/lo, CPFW adds it in sdma MQD for save/restore, KFD will read it from there. gfx 9.4.2 will still keep the way to read from memory at rptr+8. v2: read dynamic counter directly from utilization register v3: add CPFW supported version check (Harish) Signed-off-by: Eric Huang Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amd: Add register header files for DCN42B

2026-06-03T17:43:48Z

[Why & How] Add register headers for: - clk 15.0.5 - dcn 4.2.1 - dpcs 4.0.1 - nbio 7.15.5 v2: add in missing license (Alex) Reviewed-by: Harry Wentland Signed-off-by: Matthew Stewart Signed-off-by: Ray Wu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amdgpu/vpe: add new vpe v2.0.0 register offset and sh/mask

2026-05-11T20:15:51Z

New offset and sh/mask are added for vpe v2.0.0 Acked-by: Roy Chan Signed-off-by: Caden Chien Signed-off-by: Alex Deucher

drm/amd/display: Add FRL registers for DCN316

2026-05-11T20:15:28Z

Add the required FRL registers for DCN316. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add FRL registers for DCN315

2026-05-11T20:15:25Z

Add the required FRL registers for DCN315. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add FRL register for DCN303

2026-05-11T20:15:23Z

Add all the required registers to support FRL on DCN303. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add FRL register for DCN302

2026-05-11T20:15:20Z

Add the required FRL registers for DCN302. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add the necessary FRL registers for DCN314

2026-05-11T20:15:16Z

Add all the required registers to support FRL on DCN314. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher