<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/amd/pm, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/pm?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/pm?h=stable'/>
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<updated>2025-11-04T18:39:27Z</updated>
<entry>
<title>drm/amdgpu/smu: Handle S0ix for vangogh</title>
<updated>2025-11-04T18:39:27Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-10-24T17:08:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7c5609b72bfe57d8c601d9561e0d2551b605c017'/>
<id>urn:sha1:7c5609b72bfe57d8c601d9561e0d2551b605c017</id>
<content type='text'>
Fix the flows for S0ix.  There is no need to stop
rlc or reintialize PMFW in S0ix.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4659
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reported-by: Antheas Kapenekakis &lt;lkml@antheas.dev&gt;
Tested-by: Antheas Kapenekakis &lt;lkml@antheas.dev&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit fd39b5a5830d8f2553e0c09d4d50bdff28b10080)
Cc: &lt;stable@vger.kernel.org&gt; # c81f5cebe849: drm/amdgpu: Drop PMFW RLC notifier from amdgpu_device_suspend()
Cc: &lt;stable@vger.kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Drop PMFW RLC notifier from amdgpu_device_suspend()</title>
<updated>2025-11-04T18:28:20Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2025-10-26T04:29:36Z</published>
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<id>urn:sha1:c81f5cebe849a2beeed4c8f2b06a58dfc02d5350</id>
<content type='text'>
For S3 on vangogh, PMFW needs to be notified before the
driver powers down RLC.  This already happens in smu_disable_dpms()
so drop the superfluous call in amdgpu_device_suspend().

Co-developed-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mario Limonciello (AMD) &lt;superm1@kernel.org&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 960e30a61e1a7ca5341a6cf9481e770e1cda24aa)
</content>
</entry>
<entry>
<title>drm/amd/pm: fix missing device_attr cleanup in amdgpu_pm_sysfs_init()</title>
<updated>2025-11-04T18:18:05Z</updated>
<author>
<name>Yang Wang</name>
<email>kevinyang.wang@amd.com</email>
</author>
<published>2025-10-30T05:06:24Z</published>
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<id>urn:sha1:37e3567dee273f68726373b342b38234bafe4cf9</id>
<content type='text'>
Use the correct label to complete all cleanup work.

Fixes: 4d154b1ca580 ("drm/amd/pm: Add support for DPM policies")
Fixes: 25e82f2e2c59 ("drm/amd/pm: Add temperature metrics sysfs entry")
Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 4c4c138a1c86775c4d47e24f26357a1f8b64d0a3)
</content>
</entry>
<entry>
<title>drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Iceland</title>
<updated>2025-10-28T15:02:19Z</updated>
<author>
<name>John Smith</name>
<email>itistotalbotnet@gmail.com</email>
</author>
<published>2025-10-21T09:09:09Z</published>
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<id>urn:sha1:501672e3c1576aa9a8364144213c77b98a31a42c</id>
<content type='text'>
Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18aafc59b106 ("drm/amd/powerplay: implement fw related smu interface for iceland.")
Signed-off-by: John Smith &lt;itistotalbotnet@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit 92b0a6ae6672857ddeabf892223943d2f0e06c97)
</content>
</entry>
<entry>
<title>drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Fiji</title>
<updated>2025-10-28T15:02:13Z</updated>
<author>
<name>John Smith</name>
<email>itistotalbotnet@gmail.com</email>
</author>
<published>2025-10-21T09:08:13Z</published>
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<id>urn:sha1:07a13f913c291d6ec72ee4fc848d13ecfdc0e705</id>
<content type='text'>
Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18edef19ea44 ("drm/amd/powerplay: implement fw image related smu interface for Fiji.")
Signed-off-by: John Smith &lt;itistotalbotnet@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit c52238c9fb414555c68340cd80e487d982c1921c)
</content>
</entry>
<entry>
<title>drm/amd/pm: fix smu table id bound check issue in smu_cmn_update_table()</title>
<updated>2025-10-28T15:02:03Z</updated>
<author>
<name>Yang Wang</name>
<email>kevinyang.wang@amd.com</email>
</author>
<published>2025-10-22T06:12:21Z</published>
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<id>urn:sha1:238d468d3ed18a324bb9d8c99f18c665dbac0511</id>
<content type='text'>
'table_index' is a variable defined by the smu driver (kmd)
'table_id' is a variable defined by the hw smu (pmfw)

This code should use table_index as a bounds check.

Fixes: caad2613dc4bd ("drm/amd/powerplay: move table setting common code to smu_cmn.c")
Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
(cherry picked from commit fca0c66b22303de0d1d6313059baf4dc960a4753)
</content>
</entry>
<entry>
<title>drm/amd/powerplay: Fix CIK shutdown temperature</title>
<updated>2025-10-13T18:14:15Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-10-13T06:06:42Z</published>
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<id>urn:sha1:6917112af2ba36c5f19075eb9f2933ffd07e55bf</id>
<content type='text'>
Remove extra multiplication.

CIK GPUs such as Hawaii appear to use PP_TABLE_V0 in which case
the shutdown temperature is hardcoded in smu7_init_dpm_defaults
and is already multiplied by 1000. The value was mistakenly
multiplied another time by smu7_get_thermal_temperature_range.

Fixes: 4ba082572a42 ("drm/amd/powerplay: export the thermal ranges of VI asics (V2)")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1676
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Disable MCLK switching on SI at high pixel clocks</title>
<updated>2025-10-13T18:14:14Z</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-09-26T18:26:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5c05bcf6ae7732da1bd4dc1958d527b5f07f216a'/>
<id>urn:sha1:5c05bcf6ae7732da1bd4dc1958d527b5f07f216a</id>
<content type='text'>
On various SI GPUs, a flickering can be observed near the bottom
edge of the screen when using a single 4K 60Hz monitor over DP.
Disabling MCLK switching works around this problem.

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Disable VCN queue reset on SMU v13.0.6 due to regression</title>
<updated>2025-10-07T18:09:19Z</updated>
<author>
<name>Jesse.Zhang</name>
<email>Jesse.Zhang@amd.com</email>
</author>
<published>2025-10-04T14:39:24Z</published>
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<id>urn:sha1:bd8acfcfce7d711372c2c45f4c5e24ea650c26bf</id>
<content type='text'>
Disable VCN reset capability for the program 4 as it's
causing regressions.

Fixes: 9d20f37a106f ("drm/amd/pm: Add VCN reset support for SMU v13.0.6")
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Jesse Zhang &lt;jesse.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: Avoid interface mismatch messaging</title>
<updated>2025-10-07T18:09:19Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2025-09-19T05:34:44Z</published>
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<id>urn:sha1:4538a93bbbf104d7b7ce769bec48ff360bce583b</id>
<content type='text'>
PMFW interface version is not used by some IP implementations like SMU
v13.0.6/12, instead rely on PMFW version checks. Avoid the log if
interface version is not used.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
