<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/amd/ras, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/ras?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd/ras?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2026-08-06T16:46:23Z</updated>
<entry>
<title>drm/amd/ras: Handle the lack of mca address case for uniras</title>
<updated>2026-08-06T16:46:23Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2026-07-29T07:51:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=bbda86fdf2e4fabef5db977a04b4d0d9d69396ae'/>
<id>urn:sha1:bbda86fdf2e4fabef5db977a04b4d0d9d69396ae</id>
<content type='text'>
For specific old eeprom data, mca address is not stored, get mca
address from physical address(pa) and then convert it into pa in
current nps mode.
Also set cur_nps early so the record carries the target nps even
when the conversion returns early.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: add get_die_id for uniras umc v12</title>
<updated>2026-08-06T16:46:18Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2026-07-27T07:39:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=220b9c3ad727b9a723360e950b3c67990210bb51'/>
<id>urn:sha1:220b9c3ad727b9a723360e950b3c67990210bb51</id>
<content type='text'>
For legacy ras eeprom format(only existed on nps1 system), die id
(node instance) is not stored, we get it from mca address and
physical address (pa) here, and now we can calculate pa in any
nps mode for legacy ras eeprom data as well.
It only applies to num_umc == 16 / UMC_VRAM_TYPE_HBM parts.

Also factor out __ras_umc_eeprom_rec2nps_addr() so the die id can
be passed in.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: track debug mode for query mode</title>
<updated>2026-08-06T16:45:50Z</updated>
<author>
<name>Xiang Liu</name>
<email>xiang.liu@amd.com</email>
</author>
<published>2026-08-04T14:50:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=08bb824ae3fc73efd453cb303fdec5938ddc8aea'/>
<id>urn:sha1:08bb824ae3fc73efd453cb303fdec5938ddc8aea</id>
<content type='text'>
The RAS manager uses the rascore debug mode setting to control whether
MCA data is read directly or collected through PMFW MCA polling and
ClearMcaOnRead. Track that debug mode state in ras_mgr so
amdgpu_ras_get_error_query_mode() can classify queries as direct or
firmware-backed.

Limit the PMFW polling wait in recovery to firmware-backed MODE1 fatal
recovery so other reset paths, such as MODE2, do not pay the delay
unnecessarily.

Signed-off-by: Xiang Liu &lt;xiang.liu@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: move some umc v12 specific functions to ras_umc.c</title>
<updated>2026-08-06T16:44:36Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2026-07-27T03:15:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2844ade998974bc2b745e78bda8fffbab6143612'/>
<id>urn:sha1:2844ade998974bc2b745e78bda8fffbab6143612</id>
<content type='text'>
So we can reuse these functions across different ASICs.
In order to simplify code, rename some functions as well.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: rename core ras_* files and update include guards</title>
<updated>2026-08-06T13:25:58Z</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2026-07-30T06:12:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d95700604fbc6fd7534303796d005e6efbd1d591'/>
<id>urn:sha1:d95700604fbc6fd7534303796d005e6efbd1d591</id>
<content type='text'>
Rename selected RAS core source and header filenames to drop
redundant ras_ prefixes in file names only.

Update related build object names, header include references, and
include guard macros in renamed headers.

Function/type prefixes and runtime behavior are unchanged.

No functional change intended.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: rename rascore directory to core</title>
<updated>2026-08-06T13:25:11Z</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2026-07-29T09:57:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=67465d53d8814197f4332efd549a64817dc6e8bd'/>
<id>urn:sha1:67465d53d8814197f4332efd549a64817dc6e8bd</id>
<content type='text'>
Rename the RAS core directory from rascore to core and update
build-path references accordingly.

The change is mechanical and done with git rename semantics so
history tracking is preserved.

No functional change intended.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: add device lost check to early exit psp cmd wait loop</title>
<updated>2026-07-28T23:17:32Z</updated>
<author>
<name>Ce Sun</name>
<email>cesun102@amd.com</email>
</author>
<published>2026-07-24T04:03:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9ba8e75d2ee850294be33afc6aeba6ecdb95a6c6'/>
<id>urn:sha1:9ba8e75d2ee850294be33afc6aeba6ecdb95a6c6</id>
<content type='text'>
Add device lost status check in PSP fence wait loop to exit
polling early when GPU device lost

Signed-off-by: Ce Sun &lt;cesun102@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/ras: use vram_base_offset for UMC inject address</title>
<updated>2026-07-28T23:17:31Z</updated>
<author>
<name>Stanley.Yang</name>
<email>Stanley.Yang@amd.com</email>
</author>
<published>2026-07-14T09:45:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=149f894a2a8bac181af7b979180e7578e2190bb0'/>
<id>urn:sha1:149f894a2a8bac181af7b979180e7578e2190bb0</id>
<content type='text'>
Cover both XGMI hive offset and A+A platform MC FB offset in one calculation.

Signed-off-by: Stanley.Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: detect old ras eeprom format</title>
<updated>2026-07-28T22:52:39Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2026-07-08T10:19:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=47a71f452c857596e896c5b4b1cde01c8e2c38f5'/>
<id>urn:sha1:47a71f452c857596e896c5b4b1cde01c8e2c38f5</id>
<content type='text'>
Handler of some formats will be implemented in the future.

UMC_CHANNEL_IDX_V2 is a flag to indicate v2 format channel index stored
in eeprom, the flag was retired in v3 and save_nps is introduced in v3,
so they have no conflict.

eeprom format v1: store channel index within a umc instance in eeprom
    range in UMC v12: 0 ~ 7
eeprom format v2: store global channel index in eeprom
    range in UMC v12: 0 ~ 127

v2: change the bit range of save_nps from [40:47] to [40:46],
    UMC_CHANNEL_IDX_V2 use bit 47.

    use RAS_DEV_WARN_RATELIMITED for retire record check, avoid log
    noise.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/ras: update flip bit setting for uniras</title>
<updated>2026-07-28T22:52:07Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2026-07-06T09:21:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0827279ac10c3a49c981f727e0a61dfb6553e902'/>
<id>urn:sha1:0827279ac10c3a49c981f727e0a61dfb6553e902</id>
<content type='text'>
The flip bit setting is different if umc number is 8, only NPS1 and
NPS2 are supported in this mode.

Note: the typical value of umc number is 16, and it can only be 8 or 16
on umc v12.

v2: if other umc number is encountered, default setting will be
used.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
