<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/amd, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/amd?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-10T19:38:28Z</updated>
<entry>
<title>Merge tag 'drm-next-2020-04-10' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2020-04-10T19:38:28Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-04-10T19:38:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=21c5b3c6d7579944d21ff268f241d6bec425a9b4'/>
<id>urn:sha1:21c5b3c6d7579944d21ff268f241d6bec425a9b4</id>
<content type='text'>
Pull more drm fixes from Dave Airlie:
 "As expected, more fixes did turn up in the latter part of the week.

  The drm_local_map build regression fix is here, along with temporary
  disabling of the hugepage work due to some amdgpu related crashes.

  Otherwise it's just a bunch of i915, and amdgpu fixes.

  legacy:
   - fix drm_local_map.offset type

  ttm:
   - temporarily disable hugepages to debug amdgpu problems.

  prime:
   - fix sg extraction

  amdgpu:
   - Various Renoir fixes
   - Fix gfx clockgating sequence on gfx10
   - RAS fixes
   - Avoid MST property creation after registration
   - Various cursor/viewport fixes
   - Fix a confusing log message about optional firmwares

  i915:
   - Flush all the reloc_gpu batch (Chris)
   - Ignore readonly failures when updating relocs (Chris)
   - Fill all the unused space in the GGTT (Chris)
   - Return the right vswing table (Jose)
   - Don't enable DDI IO power on a TypeC port in TBT mode for ICL+ (Imre)

  analogix_dp:
   - probe fix

  virtio:
   - oob fix in object create"

* tag 'drm-next-2020-04-10' of git://anongit.freedesktop.org/drm/drm: (34 commits)
  drm/ttm: Temporarily disable the huge_fault() callback
  drm/bridge: analogix_dp: Split bind() into probe() and real bind()
  drm/legacy: Fix type for drm_local_map.offset
  drm/amdgpu/display: fix warning when compiling without debugfs
  drm/amdgpu: unify fw_write_wait for new gfx9 asics
  drm/amd/powerplay: error out on forcing clock setting not supported
  drm/amdgpu: fix gfx hang during suspend with video playback (v2)
  drm/amd/display: Check for null fclk voltage when parsing clock table
  drm/amd/display: Acknowledge wm_optimized_required
  drm/amd/display: Make cursor source translation adjustment optional
  drm/amd/display: Calculate scaling ratios on every medium/full update
  drm/amd/display: Program viewport when source pos changes for DCN20 hw seq
  drm/amd/display: Fix incorrect cursor pos on scaled primary plane
  drm/amd/display: change default pipe_split policy for DCN1
  drm/amd/display: Translate cursor position by source rect
  drm/amd/display: Update stream adjust in dc_stream_adjust_vmin_vmax
  drm/amd/display: Avoid create MST prop after registration
  drm/amdgpu/psp: dont warn on missing optional TA's
  drm/amdgpu: update RAS related dmesg print
  drm/amdgpu: resolve mGPU RAS query instability
  ...
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fix warning when compiling without debugfs</title>
<updated>2020-04-08T21:53:11Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-04-08T13:30:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7e7ea24f0b46cd3078bc9af29d1c1aced89d1c8e'/>
<id>urn:sha1:7e7ea24f0b46cd3078bc9af29d1c1aced89d1c8e</id>
<content type='text'>
fixes unused variable warning.

Reported-by: Eric Biggers &lt;ebiggers@kernel.org&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Mikita Lipski &lt;mikita.lipski@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: unify fw_write_wait for new gfx9 asics</title>
<updated>2020-04-08T21:52:38Z</updated>
<author>
<name>Aaron Liu</name>
<email>aaron.liu@amd.com</email>
</author>
<published>2020-04-07T09:46:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2960758cce2310774de60bbbd8d6841d436c54d9'/>
<id>urn:sha1:2960758cce2310774de60bbbd8d6841d436c54d9</id>
<content type='text'>
Make the fw_write_wait default case true since presumably all new
gfx9 asics will have updated firmware. That is using unique WAIT_REG_MEM
packet with opration=1.

Signed-off-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Tested-by: Aaron Liu &lt;aaron.liu@amd.com&gt;
Tested-by: Yuxian Dai &lt;Yuxian.Dai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/powerplay: error out on forcing clock setting not supported</title>
<updated>2020-04-08T21:51:54Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2020-04-03T05:19:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3abd1e95e0b0aa816d4dd63cac33a423afb4a7f2'/>
<id>urn:sha1:3abd1e95e0b0aa816d4dd63cac33a423afb4a7f2</id>
<content type='text'>
For Arcturus, forcing clock to some specific level is not supported
with 54.18 and onwards SMU firmware. As according to firmware team,
they adopt new gfx dpm tuned parameters which can cover all the use
case in a much smooth way. Thus setting through driver interface
is not needed and maybe do a disservice.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix gfx hang during suspend with video playback (v2)</title>
<updated>2020-04-08T21:51:03Z</updated>
<author>
<name>Prike Liang</name>
<email>Prike.Liang@amd.com</email>
</author>
<published>2020-04-07T12:21:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=487eca11a321ef33bcf4ca5adb3c0c4954db1b58'/>
<id>urn:sha1:487eca11a321ef33bcf4ca5adb3c0c4954db1b58</id>
<content type='text'>
The system will be hang up during S3 suspend because of SMU is pending
for GC not respose the register CP_HQD_ACTIVE access request.This issue
root cause of accessing the GC register under enter GFX CGGPG and can
be fixed by disable GFX CGPG before perform suspend.

v2: Use disable the GFX CGPG instead of RLC safe mode guard.

Signed-off-by: Prike Liang &lt;Prike.Liang@amd.com&gt;
Tested-by: Mengbing Wang &lt;Mengbing.Wang@amd.com&gt;
Reviewed-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>Merge tag 'drm-next-2020-04-08' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2020-04-08T03:24:34Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-04-08T03:24:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f5e94d10e4c468357019e5c28d48499f677b284f'/>
<id>urn:sha1:f5e94d10e4c468357019e5c28d48499f677b284f</id>
<content type='text'>
Pull drm fixes from Dave Airlie:
 "This is a set of fixes that have queued up, I think I might have
  another pull with some more before rc1 but I'd like to dequeue what I
  have now just in case Easter is more eggciting that expected.

  The main thing in here is a fix for a longstanding nouveau power
  management issues on certain laptops, it should help runtime
  suspend/resume for a lot of people.

  There is also a reverted patch for some drm_mm behaviour in atomic
  contexts.

  Summary:

  core:
   - revert drm_mm atomic patch
   - dt binding fixes

  fbcon:
   - null ptr error fix

  i915:
   - GVT fixes

  nouveau:
   - runpm fix
   - svm fixes

  amdgpu:
   - HDCP fixes
   - gfx10 fix
   - Misc display fixes
   - BACO fixes

  amdkfd:
   - Fix memory leak

  vboxvideo:
   - remove conflicting fbs

  vc4:
   - mode validation fix

  xen:
   - fix PTR_ERR usage"

* tag 'drm-next-2020-04-08' of git://anongit.freedesktop.org/drm/drm: (41 commits)
  drm/nouveau/kms/nv50-: wait for FIFO space on PIO channels
  drm/nouveau/nvif: protect waits against GPU falling off the bus
  drm/nouveau/nvif: access PTIMER through usermode class, if available
  drm/nouveau/gr/gp107,gp108: implement workaround for HW hanging during init
  drm/nouveau: workaround runpm fail by disabling PCI power management on certain intel bridges
  drm/nouveau/svm: remove useless SVM range check
  drm/nouveau/svm: check for SVM initialized before migrating
  drm/nouveau/svm: fix vma range check for migration
  drm/nouveau: remove checks for return value of debugfs functions
  drm/nouveau/ttm: evict other IO mappings when running out of BAR1 space
  drm/amdkfd: kfree the wrong pointer
  drm/amd/display: increase HDCP authentication delay
  drm/amd/display: Correctly cancel future watchdog and callback events
  drm/amd/display: Don't try hdcp1.4 when content_type is set to type1
  drm/amd/powerplay: move the ASIC specific nbio operation out of smu_v11_0.c
  drm/amd/powerplay: drop redundant BIF doorbell interrupt operations
  drm/amd/display: Fix dcn21 num_states
  drm/amd/display: Enable BT2020 in COLOR_ENCODING property
  drm/amd/display: LFC not working on 2.0x range monitors (v2)
  drm/amd/display: Support plane level CTM
  ...
</content>
</entry>
<entry>
<title>drm/amd/display: Check for null fclk voltage when parsing clock table</title>
<updated>2020-04-07T18:22:10Z</updated>
<author>
<name>Michael Strauss</name>
<email>michael.strauss@amd.com</email>
</author>
<published>2020-04-05T20:41:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=72f5b5a308c744573fdbc6c78202c52196d2c162'/>
<id>urn:sha1:72f5b5a308c744573fdbc6c78202c52196d2c162</id>
<content type='text'>
[WHY]
In cases where a clock table is malformed such that fclk entries have
frequencies but not voltages listed, we don't catch the error and set
clocks to 0 instead of using hardcoded values as we should.

[HOW]
Add check for clock tables fclk entry's voltage as well

Signed-off-by: Michael Strauss &lt;michael.strauss@amd.com&gt;
Reviewed-by: Eric Yang &lt;eric.yang2@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/display: Acknowledge wm_optimized_required</title>
<updated>2020-04-07T18:21:22Z</updated>
<author>
<name>Joshua Aberback</name>
<email>joshua.aberback@amd.com</email>
</author>
<published>2020-04-05T20:41:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6dbebf4da3616a14f43041b81a0881a7343ce5fc'/>
<id>urn:sha1:6dbebf4da3616a14f43041b81a0881a7343ce5fc</id>
<content type='text'>
[Why]
If dc-&gt;clk_mgr-&gt;funcs-&gt;are_clock_states_equal is set, then
wm_optimized_required is never checked. In that case, when going from a
higher mode to a lower mode, wm_optimized_required remains true until
the next mode change.

[How]
 - move from else-if to unconditional or

Signed-off-by: Joshua Aberback &lt;joshua.aberback@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Reviewed-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Make cursor source translation adjustment optional</title>
<updated>2020-04-07T18:20:45Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-04-05T20:41:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d243b6ffde7a3717c38b31dbc9c8c562f066d6ef'/>
<id>urn:sha1:d243b6ffde7a3717c38b31dbc9c8c562f066d6ef</id>
<content type='text'>
[Why]
In some usecases, like tiled display, the stream and plane configuration
can be setup in a way where the caller expects DAL to perform the
clipping, eg:

P0:
src_rect(0, 0, w, h)
dst_rect(0, 0, w, h)

P1:
src_rect(w, 0, w, h)
dst_rect(0, 0, w, h)

Cursor is enabled on both streams with the same position.

This can result in double cursor on tiled display, even though this
behavior is technically correct from the DC interface point of view.

We need a mechanism to control this dynamically.

[How]
This is something that should live in the DM layer based on detection
of the specified configuration but it's not something that we really
have enough information to deal with today.

Add a flag to the cursor position state that specifies whether we
want DC to do the translation or not and make it opt-in and let
the DM decide when to do it.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Tony Cheng &lt;Tony.Cheng@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Calculate scaling ratios on every medium/full update</title>
<updated>2020-04-07T18:20:45Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2020-04-05T20:40:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3bae20137cae6c03f58f96c0bc9f3d46f0bc17d4'/>
<id>urn:sha1:3bae20137cae6c03f58f96c0bc9f3d46f0bc17d4</id>
<content type='text'>
[Why]
If a plane isn't being actively enabled or disabled then DC won't
always recalculate scaling rects and ratios for the primary plane.

This results in only a partial or corrupted rect being displayed on
the screen instead of scaling to fit the screen.

[How]
Add back the logic to recalculate the scaling rects into
dc_commit_updates_for_stream since this is the expected place to
do it in DC.

This was previously removed a few years ago to fix an underscan issue
but underscan is still functional now with this change - and it should
be, since this is only updating to the latest plane state getting passed
in.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
