<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/etnaviv, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/etnaviv?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/etnaviv?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-03-20T17:40:44Z</updated>
<entry>
<title>drm/etnaviv: fix TS cache flushing on GPUs with BLT engine</title>
<updated>2020-03-20T17:40:44Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2020-02-26T15:27:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f232d9ec029ce3e2543b05213e2979e01e503408'/>
<id>urn:sha1:f232d9ec029ce3e2543b05213e2979e01e503408</id>
<content type='text'>
As seen in the Vivante kernel driver, most GPUs with the BLT engine have
a broken TS cache flush. The workaround is to temporarily set the BLT
command to CLEAR_IMAGE, without actually executing the clear. Apparently
this state change is enough to trigger the required TS cache flush. As
the BLT engine is completely asychronous, we also need a few more stall
states to synchronize the flush with the frontend.

Root-caused-by: Jonathan Marek &lt;jonathan@marek.ca&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: request pages from DMA32 zone when needed</title>
<updated>2020-03-20T17:40:44Z</updated>
<author>
<name>Lucas Stach</name>
<email>l.stach@pengutronix.de</email>
</author>
<published>2020-02-27T11:09:25Z</published>
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<id>urn:sha1:b72af445cd38a44553a5bcfcce5676155dcffcbb</id>
<content type='text'>
Some Vivante GPUs are found in systems that have interconnects restricted
to 32 address bits, but may have system memory mapped above the 4GB mark.
As this region isn't accessible to the GPU via DMA any GPU memory allocated
in the upper part needs to go through SWIOTLB bounce buffering. This kills
performance if it happens too often, as well as overrunning the available
bounce buffer space, as the GPU buffer may stay mapped for a long time.

Avoid bounce buffering by checking the addressing restrictions. If the
GPU is unable to access memory above the 4GB mark, request our SHM buffers
to be located in the DMA32 zone.

Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: Replace zero-length array with flexible-array member</title>
<updated>2020-03-05T11:15:46Z</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavo@embeddedor.com</email>
</author>
<published>2020-03-05T10:51:37Z</published>
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<id>urn:sha1:1442d81fef9955f362ed64b3da7a9d885cd09205</id>
<content type='text'>
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones is a flexible array member[1][2],
introduced in C99:

struct foo {
        int stuff;
        struct boo array[];
};

By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on.

Also, notice that, dynamic memory allocations won't be affected by
this change:

"Flexible array members have incomplete type, and so the sizeof operator
may not be applied. As a quirk of the original implementation of
zero-length arrays, sizeof evaluates to zero."[1]

This issue was found with the help of Coccinelle.

[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")

Signed-off-by: Gustavo A. R. Silva &lt;gustavo@embeddedor.com&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: Warn when GPU doesn't idle fast enough</title>
<updated>2020-03-03T09:58:57Z</updated>
<author>
<name>Guido Günther</name>
<email>agx@sigxcpu.org</email>
</author>
<published>2020-03-02T19:13:36Z</published>
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<id>urn:sha1:78f2bfa3181cd7ee134274aa17177dd933c69dc1</id>
<content type='text'>
If the GPU isn't idle after signalling pm_runtime_mark_last_busy() plus
waiting for the autosuspend delay there's likely something wrong with
the way we check idleness so warn about that.

Signed-off-by: Guido Günther &lt;agx@sigxcpu.org&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: Ignore MC when checking runtime suspend idleness</title>
<updated>2020-03-03T09:58:57Z</updated>
<author>
<name>Guido Günther</name>
<email>agx@sigxcpu.org</email>
</author>
<published>2020-03-02T19:13:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1a910c11d35bfacb68a3e650fbc087491e92661f'/>
<id>urn:sha1:1a910c11d35bfacb68a3e650fbc087491e92661f</id>
<content type='text'>
Without that runtime suspend is often blocked due to
etnaviv_gpu_rpm_suspend() returning -EBUSY since the FE seems to trigger
the MC in its idle loop.

Ignoring the MC bit makes the GPU suspend as expected. This was tested
on GC7000.

Signed-off-by: Guido Günther &lt;agx@sigxcpu.org&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: Consider all kwnown idle bits in debugfs</title>
<updated>2020-03-03T09:58:57Z</updated>
<author>
<name>Guido Günther</name>
<email>agx@sigxcpu.org</email>
</author>
<published>2020-03-02T19:13:34Z</published>
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<id>urn:sha1:b170455120b6a465d2b424562cafaad4a7ac94c1</id>
<content type='text'>
We were missing out on some bits the vendor kernel driver knows about.

Signed-off-by: Guido Günther &lt;agx@sigxcpu.org&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: Update idle bits</title>
<updated>2020-03-03T09:58:57Z</updated>
<author>
<name>Guido Günther</name>
<email>agx@sigxcpu.org</email>
</author>
<published>2020-03-02T19:13:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b9e352ed825844aa3b8c71b7b1ebb906b4800e6f'/>
<id>urn:sha1:b9e352ed825844aa3b8c71b7b1ebb906b4800e6f</id>
<content type='text'>
Update the state HI and common header from rnndb commit
commit 19280a95a (rnndb: Update idle bits)

Signed-off-by: Guido Günther &lt;agx@sigxcpu.org&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: Fix typo in comment</title>
<updated>2020-03-03T09:58:57Z</updated>
<author>
<name>Guido Günther</name>
<email>agx@sigxcpu.org</email>
</author>
<published>2020-03-02T19:13:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ea4ed4a55f7363ad8db1863bd536548fb7e5c6aa'/>
<id>urn:sha1:ea4ed4a55f7363ad8db1863bd536548fb7e5c6aa</id>
<content type='text'>
Use 'is' instead of 'it' so it becomes a valid sentence and
spell 'resetting' correctly.

Signed-off-by: Guido Günther &lt;agx@sigxcpu.org&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: rework perfmon query infrastructure</title>
<updated>2020-03-03T09:58:06Z</updated>
<author>
<name>Christian Gmeiner</name>
<email>christian.gmeiner@gmail.com</email>
</author>
<published>2020-02-28T10:37:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=ed1dd899baa32d47d9a93d98336472da50564346'/>
<id>urn:sha1:ed1dd899baa32d47d9a93d98336472da50564346</id>
<content type='text'>
Report the correct perfmon domains and signals depending
on the supported feature flags.

Reported-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Fixes: 9e2c2e273012 ("drm/etnaviv: add infrastructure to query perf counter")
Cc: stable@vger.kernel.org
Signed-off-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
<entry>
<title>drm/etnaviv: add hwdb entry for gc400 found in STM32</title>
<updated>2020-02-26T15:20:04Z</updated>
<author>
<name>Christian Gmeiner</name>
<email>christian.gmeiner@gmail.com</email>
</author>
<published>2020-01-06T15:16:51Z</published>
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<id>urn:sha1:f56f1579a094573104ffb0e81b623528d992b73c</id>
<content type='text'>
The information was taken from STM32 glacore driver hw database.
The entry is named as gc7000nano_0x4652.

Signed-off-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
Signed-off-by: Lucas Stach &lt;l.stach@pengutronix.de&gt;
</content>
</entry>
</feed>
