<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/gpu/drm/xe/regs, branch jd/bump-compilers</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/xe/regs?h=jd%2Fbump-compilers</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/gpu/drm/xe/regs?h=jd%2Fbump-compilers'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-09-12T14:07:15Z</updated>
<entry>
<title>drm/xe/oa: Enable Xe2+ PES disaggregation</title>
<updated>2024-09-12T14:07:15Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-09-09T16:59:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a262cc8d554217fbe67e083159584beee3ea9b11'/>
<id>urn:sha1:a262cc8d554217fbe67e083159584beee3ea9b11</id>
<content type='text'>
Enable Xe2+ PES disaggregation (for OAG) to retrieve disaggregated metrics
when disaggregated data is needed. Userspace can select whether to receive
aggregated or disaggregated metrics via the particular OA configuration it
uses (programmed via DRM_XE_OBSERVATION_OP_ADD_CONFIG).

Bspec: 61101
Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240909165933.2638765-1-ashutosh.dixit@intel.com
Cc: stable@vger.kernel.org
(cherry picked from commit fb2551a0e93897aec7fb3d4f473ebc06b146d160)
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/xe2hpg: Add Wa_14021821874</title>
<updated>2024-08-19T17:34:58Z</updated>
<author>
<name>Tejas Upadhyay</name>
<email>tejas.upadhyay@intel.com</email>
</author>
<published>2024-08-12T13:41:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8776b0234e1d008d8f19b26f6c3af1cfa6187070'/>
<id>urn:sha1:8776b0234e1d008d8f19b26f6c3af1cfa6187070</id>
<content type='text'>
Wa_14021821874 applies to xe2_hpg

V2(Himal):
  - Use space after define

Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Signed-off-by: Tejas Upadhyay &lt;tejas.upadhyay@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240812134117.813670-1-tejas.upadhyay@intel.com
(cherry picked from commit 21ff3a16e92e2fa4f906a61d148aca1423c58298)
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/bmg: implement Wa_16023588340</title>
<updated>2024-08-19T17:30:41Z</updated>
<author>
<name>Matthew Auld</name>
<email>matthew.auld@intel.com</email>
</author>
<published>2024-07-03T12:43:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=27cb2b7fec2abf310e4128137979124ead920ccb'/>
<id>urn:sha1:27cb2b7fec2abf310e4128137979124ead920ccb</id>
<content type='text'>
This involves enabling l2 caching of host side memory access to VRAM
through the CPU BAR. The main fallout here is with display since VRAM
writes from CPU can now be cached in GPU l2, and display is never
coherent with caches, so needs various manual flushing.  In the case of
fbc we disable it due to complications in getting this to work
correctly (in a later patch).

Signed-off-by: Matthew Auld &lt;matthew.auld@intel.com&gt;
Cc: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Cc: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Cc: Vinod Govindapillai &lt;vinod.govindapillai@intel.com&gt;
Reviewed-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240703124338.208220-3-matthew.auld@intel.com
(cherry picked from commit 01570b446939c3538b1aa3d059837f49fa14a3ae)
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge drm/drm-next into drm-xe-next</title>
<updated>2024-06-26T22:22:52Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2024-06-26T22:22:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8664e7637388c013f4e953371d023ec7c2d84c8d'/>
<id>urn:sha1:8664e7637388c013f4e953371d023ec7c2d84c8d</id>
<content type='text'>
Need to sync some header include that propagated through
drm-intel-next.

v2: After some changes in drm/drm-next

Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge drm/drm-next into drm-intel-next</title>
<updated>2024-06-19T08:38:31Z</updated>
<author>
<name>Jani Nikula</name>
<email>jani.nikula@intel.com</email>
</author>
<published>2024-06-19T08:38:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=d754ed2821fd9675d203cb73c4afcd593e28b7d0'/>
<id>urn:sha1:d754ed2821fd9675d203cb73c4afcd593e28b7d0</id>
<content type='text'>
Sync to v6.10-rc3.

Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/oa: Add MMIO trigger support</title>
<updated>2024-06-18T19:40:42Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-06-18T01:46:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=828a8eaf37c3fac6ba048995f55f1647a4ac542d'/>
<id>urn:sha1:828a8eaf37c3fac6ba048995f55f1647a4ac542d</id>
<content type='text'>
Add MMIO trigger support and allow-list required registers for MMIO trigger
use case. Registers are whitelisted for the lifetime of the driver but MMIO
trigger is enabled only for the duration of the stream.

Bspec: 45925, 60340, 61228

Acked-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240618014609.3233427-15-ashutosh.dixit@intel.com
</content>
</entry>
<entry>
<title>drm/xe/oa: Add OAC support</title>
<updated>2024-06-18T19:40:39Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-06-18T01:46:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=14e077f8006df9d2d7adf380f0c80e16d6a0a548'/>
<id>urn:sha1:14e077f8006df9d2d7adf380f0c80e16d6a0a548</id>
<content type='text'>
Similar to OAR, allow userspace to execute MI_REPORT_PERF_COUNT on compute
engines of a specified exec queue.

Acked-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240618014609.3233427-12-ashutosh.dixit@intel.com
</content>
</entry>
<entry>
<title>drm/xe/oa: Add OAR support</title>
<updated>2024-06-18T19:40:38Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-06-18T01:46:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2f4a730fcd2d6ae7378a67fe78797b0a3f7ca1b3'/>
<id>urn:sha1:2f4a730fcd2d6ae7378a67fe78797b0a3f7ca1b3</id>
<content type='text'>
Add OAR support to allow userspace to execute MI_REPORT_PERF_COUNT on
render engines. Configuration batches are used to program the OAR unit, as
well as modifying the render engine context image of a specified exec queue
(to have correct register values when that context switches in).

v2: Rename/refactor xe_oa_modify_self (Umesh)
v3: Move IS_MI_LRI_CMD() into xe_oa.c (Michal)

Acked-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240618014609.3233427-11-ashutosh.dixit@intel.com
</content>
</entry>
<entry>
<title>drm/xe/oa: OA stream initialization (OAG)</title>
<updated>2024-06-18T19:40:33Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-06-18T01:45:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1db9a9dc90aece0803a26a711b52a9492faefab7'/>
<id>urn:sha1:1db9a9dc90aece0803a26a711b52a9492faefab7</id>
<content type='text'>
Implement majority of OA stream initialization (as part of OA stream open)
ioctl). OAG buffer is allocated for receiving perf counter samples from
HW. OAG unit is initialized and the selected OA metric configuration is
programmed into OAG unit HW using a command/batch buffer.

Acked-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240618014609.3233427-8-ashutosh.dixit@intel.com
</content>
</entry>
<entry>
<title>drm/xe/oa/uapi: Initialize OA units</title>
<updated>2024-06-18T19:40:29Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2024-06-18T01:45:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a9f905ae7b6f29a337dda2ad773c08b92dafe9a5'/>
<id>urn:sha1:a9f905ae7b6f29a337dda2ad773c08b92dafe9a5</id>
<content type='text'>
Initialize OA unit data struct's for each gt during device probe. Also
assign OA units for hardware engines.

v2: Remove XE_OA_UNIT_OAG/XE_OA_UNIT_OAM_SAMEDIA_0 enum (Umesh)
    Change mtl_oa_base to 0x13000 (Umesh)
v3: Switch to drmm_ functions and other cleanups (Michal)

Acked-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Acked-by: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20240618014609.3233427-5-ashutosh.dixit@intel.com
</content>
</entry>
</feed>
