wireguard-linux/drivers/hwtracing/intel_th/intel_th.h, branch jd/orphan-parallel

intel_th: Disallow multi mode on devices where it's broken

2020-03-18T10:28:22Z

Some versions of Intel TH have an issue that prevents the multi mode of MSU from working correctly, resulting in no trace data and potentially stuck MSU pipeline. Disable multi mode on such devices. Signed-off-by: Alexander Shishkin Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200317062215.15598-2-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman

intel_th: Fix freeing IRQs

2019-12-17T14:45:58Z

Commit aac8da65174a ("intel_th: msu: Start handling IRQs") implicitly relies on the use of devm_request_irq() to subsequently free the irqs on device removal, but in case of the pci_free_irq_vectors() API, the handlers need to be freed before it is called. Therefore, at the moment the driver's remove path trips a BUG_ON(irq_has_action()): > kernel BUG at drivers/pci/msi.c:375! > invalid opcode: 0000 1 SMP > CPU: 2 PID: 818 Comm: rmmod Not tainted 5.5.0-rc1+ #1 > RIP: 0010:free_msi_irqs+0x67/0x1c0 > pci_disable_msi+0x116/0x150 > pci_free_irq_vectors+0x1b/0x20 > intel_th_pci_remove+0x22/0x30 [intel_th_pci] > pci_device_remove+0x3e/0xb0 > device_release_driver_internal+0xf0/0x1c0 > driver_detach+0x4c/0x8f > bus_remove_driver+0x5c/0xd0 > driver_unregister+0x31/0x50 > pci_unregister_driver+0x40/0x90 > intel_th_pci_driver_exit+0x10/0xad6 [intel_th_pci] > __x64_sys_delete_module+0x147/0x290 > ? exit_to_usermode_loop+0xd7/0x120 > do_syscall_64+0x57/0x1b0 > entry_SYSCALL_64_after_hwframe+0x44/0xa9 Fix this by explicitly freeing irqs before freeing the vectors. We keep using the devm_* variants because they are still useful in early error paths. Signed-off-by: Alexander Shishkin Reviewed-by: Andy Shevchenko Fixes: aac8da65174a ("intel_th: msu: Start handling IRQs") Reported-by: Ammy Yi Tested-by: Ammy Yi Cc: stable@vger.kernel.org # v5.2+ Link: https://lore.kernel.org/r/20191217115527.74383-4-alexander.shishkin@linux.intel.com Signed-off-by: Greg Kroah-Hartman

intel_th: Add switch triggering support

2019-05-03T16:16:21Z

Add support for asserting window switch trigger when tracing to MSU output ports. This allows for software controlled switching between windows of the MSU buffer, which can be used for double buffering while exporting the trace data further from the MSU. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: msu: Factor out pipeline draining

2019-05-03T16:16:21Z

The code that waits for the pipeline empty condition of the MSU is currently called in the path that disables the trace. We will also need this in the window switch trigger sequence. Therefore, factor out this code and make it accessible to the GTH device. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: Only report useful IRQs to subdevices

2019-05-03T16:14:30Z

The only type of IRQ triggering event that is useful to us at the moment is the "last block" interrupt of the MSU. This interrupt can only be enabled via "MINTCTL" register that doesn't exist in earlier version of the Intel TH. Enumerate the presence of MINTCTL via per-device driver data structure and only instantiate the IRQ resource for subdevices if this capability is present. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: msu: Start handling IRQs

2019-05-03T16:14:30Z

We intend to use the interrupt to detect Last Block condition in the MSU driver, which we can use for double-buffering software-managed data transfers. Add an interrupt handler to the MSU driver. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: pci: Use MSI interrupt signalling

2019-05-03T16:14:30Z

Since Intel TH is capable of MSI interrupt signalling, make use of it. The way it works is, each of the 7 interrupt triggering events has its own vector in this mode, as opposed to interrupt line delivery, where all events are signalled via the same line. Failing to enable MSI, the driver falls back to using an interrupt line. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: Communicate IRQ via resource

2019-05-03T16:14:29Z

Currently, the IRQ is passed between the glue layers and the core as a separate argument, while the MMIO resources are passed as resources. This also limits the number of IRQs thus used to one, while the current versions of Intel TH use a different MSI vector for each interrupt triggering event, of which there are 7. Change this to pass IRQ in the resources array. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: Add "rtit" source device

2019-05-03T16:14:29Z

In some versions of Intel TH, the Software Trace Hub (STH) has a second MMIO BAR dedicated to the input from Intel PT. This calls for a new subdevice that will be enumerated if the corresponding BAR is present. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman

intel_th: Rework resource passing between glue layers and core

2019-05-03T16:14:29Z

Currently, MMIO resource numbers in the TH driver core correspond to PCI BAR numbers, because in the beginning there was only the PCI glue layer. This created some confusion when the ACPI glue layer was added. To avoid confusion and remove glue-specific code from the driver core, split the resource indices between core and glue layers and change the API so that the driver core receives the MMIO resources in the same fixed order. At the same time, make the IRQ always be a parameter to intel_th_alloc() instead of sometimes passing it as a resource. Signed-off-by: Alexander Shishkin Signed-off-by: Greg Kroah-Hartman