<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/hwtracing, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/hwtracing?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/hwtracing?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-10-05T10:43:54Z</updated>
<entry>
<title>intel_th: pci: Add Alder Lake CPU support</title>
<updated>2020-10-05T10:43:54Z</updated>
<author>
<name>Alexander Shishkin</name>
<email>alexander.shishkin@linux.intel.com</email>
</author>
<published>2020-10-05T07:13:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=9f126c56b9d645e7014777d7d37d74eedc4e3137'/>
<id>urn:sha1:9f126c56b9d645e7014777d7d37d74eedc4e3137</id>
<content type='text'>
This adds support for the Trace Hub in Alder Lake CPU.

Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-9-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>intel_th: pci: Add Alder Lake-S support</title>
<updated>2020-10-05T10:43:54Z</updated>
<author>
<name>Alexander Shishkin</name>
<email>alexander.shishkin@linux.intel.com</email>
</author>
<published>2020-10-05T07:13:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=951e4d71a8fa84b76aff8181d288af025f250a3c'/>
<id>urn:sha1:951e4d71a8fa84b76aff8181d288af025f250a3c</id>
<content type='text'>
This adds support for the Trace Hub in Alder Lake-S.

Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-8-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>stm class: ftrace: Use different channel accroding to CPU</title>
<updated>2020-10-05T10:43:54Z</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-10-05T07:13:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b8f8534b10b6ee3cec5e49682d7e0c4796cdccea'/>
<id>urn:sha1:b8f8534b10b6ee3cec5e49682d7e0c4796cdccea</id>
<content type='text'>
To avoid mixup of packets from differnt ftrace packets simultaneously,
use different channel for packets from different CPU.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-7-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>stm class: ftrace: Enable supported trace export flag</title>
<updated>2020-10-05T10:43:54Z</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-10-05T07:13:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=e8ecea3017385858be0ba5640b3b364586743c6b'/>
<id>urn:sha1:e8ecea3017385858be0ba5640b3b364586743c6b</id>
<content type='text'>
Set flags for trace_export. Export function trace, event trace
and trace marker to stm.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Reviewed-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-6-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>stm class: ftrace: Change dependency to TRACING</title>
<updated>2020-10-05T10:43:53Z</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-10-05T07:13:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=7b9749bd830848bca9179b0a16251ca3c36e82e6'/>
<id>urn:sha1:7b9749bd830848bca9179b0a16251ca3c36e82e6</id>
<content type='text'>
We will support copying event trace to STM. Change
STM_SOURCE_FTRACE to depend on TRACING since we will
support multiple tracers.

Reviewed-by: Steven Rostedt (VMware) &lt;rostedt@goodmis.org&gt;
Reviewed-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20201005071319.78508-2-alexander.shishkin@linux.intel.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register</title>
<updated>2020-09-28T17:47:42Z</updated>
<author>
<name>Sai Prakash Ranjan</name>
<email>saiprakash.ranjan@codeaurora.org</email>
</author>
<published>2020-09-28T16:35:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3477326277451000bc667dfcc4fd0774c039184c'/>
<id>urn:sha1:3477326277451000bc667dfcc4fd0774c039184c</id>
<content type='text'>
In commit f188b5e76aae ("coresight: etm4x: Save/restore state
across CPU low power states"), mistakenly TRCVMIDCCTLR1 register
value was saved in trcvmidcctlr0 state variable which is used to
store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then
same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1
in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state
variable available for TRCVMIDCCTLR1, so use it.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-26-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: core: Allow the coresight core driver to be built as a module</title>
<updated>2020-09-28T17:47:42Z</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-09-28T16:35:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8e264c52e1dab8a7c1e036222ef376c8920c3423'/>
<id>urn:sha1:8e264c52e1dab8a7c1e036222ef376c8920c3423</id>
<content type='text'>
Enhance coresight developer's efficiency to debug coresight drivers.
- Kconfig becomes a tristate, to allow =m
- append -core to source file name to allow module to
  be called coresight by the Makefile
- modules can have only one init/exit, so we add the etm_perf
  register/unregister function calls to the core init/exit
  functions.
- add a MODULE_DEVICE_TABLE for autoloading on boot

Cc: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Cc: Leo Yan &lt;leo.yan@linaro.org&gt;
Cc: Alexander Shishkin &lt;alexander.shishkin@linux.intel.com&gt;
Cc: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Suzuki K Poulose &lt;Suzuki.Poulose@arm.com&gt;
Cc: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Cc: Russell King &lt;linux@armlinux.org.uk&gt;
Tested-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Kim Phillips &lt;kim.phillips@arm.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-25-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: catu: Allow catu drivers to be built as modules</title>
<updated>2020-09-28T17:47:42Z</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-09-28T16:35:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=a114dbea544dffa9850f3f6e79bf7d8706ddd4a5'/>
<id>urn:sha1:a114dbea544dffa9850f3f6e79bf7d8706ddd4a5</id>
<content type='text'>
Allow to build coresight-catu as modules, for ease of development.
- Kconfig becomes a tristate, to allow =m
- add catu_remove functions, for module unload
- add a MODULE_DEVICE_TABLE for autoloading on boot

Reviewed-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-24-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: tmc-etr: Add function to register catu ops</title>
<updated>2020-09-28T17:47:42Z</updated>
<author>
<name>Mian Yousaf Kaukab</name>
<email>ykaukab@suse.de</email>
</author>
<published>2020-09-28T16:35:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=66af416d9dccaba7eb4efd290b9afcac71d3eeee'/>
<id>urn:sha1:66af416d9dccaba7eb4efd290b9afcac71d3eeee</id>
<content type='text'>
Make etr_catu_buf_ops static. Instead of directly accessing it in
etr_buf_ops[], add a function to let catu driver register the ops at
runtime. Break circular dependency between tmc-etr and catu drivers.

Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Mian Yousaf Kaukab &lt;ykaukab@suse.de&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-23-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>coresight: cti: Allow cti to be built as a module</title>
<updated>2020-09-28T17:47:42Z</updated>
<author>
<name>Tingwei Zhang</name>
<email>tingwei@codeaurora.org</email>
</author>
<published>2020-09-28T16:35:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3c3fd1a14552cd9305737ab3d278d2df542a797e'/>
<id>urn:sha1:3c3fd1a14552cd9305737ab3d278d2df542a797e</id>
<content type='text'>
Allow to build coresight-cti as a module, for ease of development.

- Kconfig becomes a tristate, to allow =m
- append -core to source file name to allow module to
  be called coresight-cti by the Makefile
- add an cti_remove function, for module unload
- add a MODULE_DEVICE_TABLE for autoloading on boot
- move cti_remove_conn_xrefs to cti_remove since all sysfs links
  have gone when system calls device_release.

Reviewed-by Mike Leach &lt;mike.leach@linaro.org&gt;

Tested-by: Mike Leach &lt;mike.leach@linaro.org&gt;
Signed-off-by: Tingwei Zhang &lt;tingwei@codeaurora.org&gt;
Signed-off-by: Mathieu Poirier &lt;mathieu.poirier@linaro.org&gt;
Link: https://lore.kernel.org/r/20200928163513.70169-22-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
</feed>
