<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/iommu/generic_pt, branch stable</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/iommu/generic_pt?h=stable</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/iommu/generic_pt?h=stable'/>
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<updated>2026-08-10T07:51:52Z</updated>
<entry>
<title>iommupt: Return zero for invalid iova_to_phys() ranges</title>
<updated>2026-08-10T07:51:52Z</updated>
<author>
<name>Shuai Xue</name>
<email>xueshuai@linux.alibaba.com</email>
</author>
<published>2026-07-26T07:43:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=41cdc2a3d41b505c1dff9e6c1ab4c76d4cc1f995'/>
<id>urn:sha1:41cdc2a3d41b505c1dff9e6c1ab4c76d4cc1f995</id>
<content type='text'>
DOMAIN_NS(iova_to_phys) returns a phys_addr_t and follows the IOMMU
iova_to_phys() convention of returning 0 when there is no valid
translation.

make_range() returns a negative errno if the input IOVA cannot be
represented by this page table format. Returning that errno directly
casts it to phys_addr_t. Callers treat zero as no translation and use
non-zero values as physical addresses, so this can make them consume a
bogus physical address instead of seeing a failed translation.

Match the page-table walk failure path and return 0 for range validation
failures too.

Fixes: 9d4c274cd7d5 ("iommupt: Add iova_to_phys op")
Cc: stable@vger.kernel.org
Assisted-by: Qoder:Qwen-3.8-MAX-Preview
Signed-off-by: Shuai Xue &lt;xueshuai@linux.alibaba.com&gt;
Reviewed-by: Lu Baolu &lt;baolu.lu@linux.intel.com&gt;
Reviewed-by: Kevin Tian &lt;kevin.tian@intel.com&gt;
Reviewed-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge branches 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'rockchip', 'verisilicon', 'riscv', 'intel/vt-d', 'amd/amd-vi' and 'core' into next</title>
<updated>2026-06-12T12:57:23Z</updated>
<author>
<name>Joerg Roedel</name>
<email>joerg.roedel@amd.com</email>
</author>
<published>2026-06-12T12:57:23Z</published>
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<id>urn:sha1:dd8a3c6cd531dca5917111a94fa3074077f6ba5a</id>
<content type='text'>
</content>
</entry>
<entry>
<title>iommu_pt: add kunit config for 32-bit VA (amdv1_cfg_1)</title>
<updated>2026-05-19T08:49:03Z</updated>
<author>
<name>Ankit Soni</name>
<email>Ankit.Soni@amd.com</email>
</author>
<published>2026-04-13T14:45:20Z</published>
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<id>urn:sha1:d9f759704b546a46649f8c51d5e9b63e96afdbae</id>
<content type='text'>
Add test coverage for small VAs (32‑bit) starting at level 2 by enabling
the AMDv1 KUnit configuration. This limits level expansion because the
starting level can accommodate only the maximum virtual address requested.

Reviewed-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Signed-off-by: Ankit Soni &lt;Ankit.Soni@amd.com&gt;
Reviewed-by: Vasant Hegde &lt;vasant.hegde@amd.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommu_pt: support small VA for AMDv1</title>
<updated>2026-05-19T08:49:03Z</updated>
<author>
<name>Ankit Soni</name>
<email>Ankit.Soni@amd.com</email>
</author>
<published>2026-04-13T14:45:19Z</published>
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<id>urn:sha1:5240dab55b51c5f14448643ad044a5643f5b569b</id>
<content type='text'>
When hardware/VM request a small VA limit, the generic page-table code
clears PT_FEAT_DYNAMIC_TOP. This later causes domain initialization to
fail with -EOPNOTSUPP.

Remove the clearing so init succeeds when the VA fits in the starting
level and no top-level growth is needed.

Signed-off-by: Ankit Soni &lt;Ankit.Soni@amd.com&gt;
Reviewed-by: Vasant Hegde &lt;vasant.hegde@amd.com&gt;
Reviewed-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommu_pt: Fix pgsize_bitmap calculation in get_info for smaller vasz's</title>
<updated>2026-05-19T08:49:02Z</updated>
<author>
<name>Ankit Soni</name>
<email>Ankit.Soni@amd.com</email>
</author>
<published>2026-04-13T14:45:18Z</published>
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<id>urn:sha1:04f1f4bf30b8b00e9eca7143dea094ccc2ec478e</id>
<content type='text'>
To properly enforce the domain VA limit, clamp pgsize_bitmap using the
requested max_vasz_lg2 in get_info().
Apply the same VA limit as get_info() in the kunit possible_sizes test so
assertions stay consistent with the domain bitmap.

Suggested-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Signed-off-by: Ankit Soni &lt;Ankit.Soni@amd.com&gt;
Reviewed-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommu/riscv: Enable PT_FEAT_DETAILED_GATHER and pass gather to iotlb_inval</title>
<updated>2026-05-19T08:48:08Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@nvidia.com</email>
</author>
<published>2026-05-08T14:53:03Z</published>
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<id>urn:sha1:db1aad42ca8b37437846078dfc405abda7868261</id>
<content type='text'>
RISC-V can use the information from PT_FEAT_DETAILED_GATHER to
compute the best stride to generate the single TLB invalidations.

Pass the gather down to the lower functions and create a full-range
gather for the flush-all callback.

Reviewed-by: Tomasz Jeznach &lt;tjeznach@rivosinc.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Tested-by: Andrew Jones &lt;andrew.jones@oss.qualcomm.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommupt: Add PT_FEAT_DETAILED_GATHER</title>
<updated>2026-05-19T08:45:38Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@nvidia.com</email>
</author>
<published>2026-05-08T14:53:02Z</published>
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<id>urn:sha1:89792629d4b260104555f9719ac84c1afc9a2012</id>
<content type='text'>
Generating the ARM SMMUv3 and RISC-V invalidation commands optimally
requires some additional details from iommupt:

- leaf_levels_bitmap is used to compute the ARM Range Invalidation
  Table Top Level hint

- leaf_levels_bitmap is also used to compute the stride when
  generating single invalidations to invalidate once per leaf

- table_levels_bitmap also computes the ARM TTL for future cases when
  there are no leaves

Put these under a feature since only two drivers need to calculate
them.

This is also useful for the coming kunit iotlb invalidation test to
know more about what invalidation is happening.

Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Reviewed-by: Pranjal Shrivastava &lt;praan@google.com&gt;
Tested-by: Andrew Jones &lt;andrew.jones@oss.qualcomm.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommupt: Add struct iommupt_pending_gather</title>
<updated>2026-05-19T08:45:38Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@nvidia.com</email>
</author>
<published>2026-05-08T14:53:01Z</published>
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<id>urn:sha1:f0e4b7f5f87578cdd2d0f1e866183adc10d33b85</id>
<content type='text'>
Add a struct to keep track of all the things that are pending to be
merged into the gather. The way gather merging works, the pending
range is checked against the current gather, and the current gather
can be flushed before the pending things are added.

Thus, if new things have to be recorded in the gather they need to be
kept in the pending struct until after the gather is optionally
flushed.

The next patch adds new items to the gather and the pending struct.

Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Reviewed-by: Pranjal Shrivastava &lt;praan@google.com&gt;
Tested-by: Andrew Jones &lt;andrew.jones@oss.qualcomm.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommupt: Fixup build warning by using BIT_ULL() for RISCVPT_NC/IO</title>
<updated>2026-05-15T05:33:17Z</updated>
<author>
<name>Fangyu Yu</name>
<email>fangyu.yu@linux.alibaba.com</email>
</author>
<published>2026-05-12T14:43:30Z</published>
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<id>urn:sha1:e861aaea2f478d23e9ee05edd4fd403f40ac75fa</id>
<content type='text'>
Fix build warning on 32-bit configurations by using BIT_ULL() for
RISCVPT_NC and RISCVPT_IO.

Fixes: 6c21eb174c6c ("iommupt: Encode IOMMU_MMIO/IOMMU_CACHE via RISC-V Svpbmt bits")
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202605121350.wZxB51k0-lkp@intel.com/
Signed-off-by: Fangyu Yu &lt;fangyu.yu@linux.alibaba.com&gt;
Reviewed-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
<entry>
<title>iommupt: Fix the end_index calculation in __map_range_leaf()</title>
<updated>2026-05-15T05:29:16Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@nvidia.com</email>
</author>
<published>2026-05-12T16:46:17Z</published>
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<id>urn:sha1:58829512ad461af8f35941069c209941e3a97b65</id>
<content type='text'>
Sashiko noticed a mismatch of units in this math: num_leaves is
actually the number of leaf *entries* (so a 16-item contiguous leaf
is one num_leaves), while index is in items. The mismatch in maths
causes __map_range_leaf() to exit early instead of efficiently
filling a larger range of contiguous PTEs.

The early exit is caught by the functions above and then
__map_range_leaf() is re-invoked, so there is no functional issue.

Correct the misuse of units by adjusting num_leaves with the leaf
size and avoid the performance cost of looping externally.

There are also some mismatched types for num_leaves; simplify
things to remove the duplicated calculations.

Fixes: d6c65b0fd621 ("iommupt: Avoid rewalking during map")
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Reviewed-by: Samiullah Khawaja &lt;skhawaja@google.com&gt;
Reviewd-by: Pranjal Shrivastava &lt;praan@google.com&gt;
Tested-by: Josua Mayer &lt;josua@solid-run.com&gt;
Signed-off-by: Joerg Roedel &lt;joerg.roedel@amd.com&gt;
</content>
</entry>
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