wireguard-linux/drivers/irqchip/Makefile, branch jd/unified-crypt-queue

irqchip: Add driver for Loongson-3 HyperTransport PIC controller

2020-03-25T09:56:43Z

This controller appeared on Loongson-3 family of chips to receive interrupts from PCH PIC. It is a I8259 with optimized interrupt polling flow. We can poll interrupt number from HT vector directly but still have to follow standard I8259 routines to mask, unmask and EOI. Signed-off-by: Jiaxun Yang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Reviewed-by: Marc Zyngier Signed-off-by: Thomas Bogendoerfer

irqchip: Add driver for Loongson I/O Local Interrupt Controller

2020-03-25T09:53:47Z

This controller appeared on Loongson family of chips as the primary package interrupt source. Signed-off-by: Jiaxun Yang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Reviewed-by: Marc Zyngier Signed-off-by: Thomas Bogendoerfer

irqchip: Add NXP INTMUX interrupt multiplexer support

2020-01-20T19:10:05Z

The Interrupt Multiplexer (INTMUX) expands the number of peripherals that can interrupt the core: * The INTMUX has 8 channels that are assigned to 8 NVIC interrupt slots. * Each INTMUX channel can receive up to 32 interrupt sources and has 1 interrupt output. * The INTMUX routes the interrupt sources to the interrupt outputs. Signed-off-by: Shengjiu Wang Signed-off-by: Joakim Zhang Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20200117060653.27485-3-qiangqing.zhang@nxp.com

irqchip: Define EXYNOS_IRQ_COMBINER

2020-01-20T19:10:05Z

This patch is written to clean up dependency of ARCH_EXYNOS Not all exynos device have IRQ_COMBINER, especially aarch64 EXYNOS but it is built for all exynos devices. Thus add the config for EXYNOS_IRQ_COMBINER remove direct dependency between ARCH_EXYNOS and exynos-combiner.c and only selected on the aarch32 devices Signed-off-by: Hyunki Koo Signed-off-by: Marc Zyngier Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20191224211108.7128-1-hyunki00.koo@gmail.com

irqchip: Add Aspeed SCU interrupt controller

2020-01-20T19:10:04Z

The Aspeed SOCs provide some interrupts through the System Control Unit registers. Add an interrupt controller that provides these interrupts to the system. Signed-off-by: Eddie James Signed-off-by: Marc Zyngier Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/1579123790-6894-3-git-send-email-eajames@linux.ibm.com

irqchip: Add support for Layerscape external interrupt lines

2019-11-10T18:47:49Z

The LS1021A allows inverting the polarity of six interrupt lines IRQ[0:5] via the scfg_intpcr register, effectively allowing IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to check the type, set the relevant bit in INTPCR accordingly, and fixup the type argument before calling the GIC's irq_set_type. In fact, the power-on-reset value of the INTPCR register on the LS1021A is so that all six lines have their polarity inverted. Hence any hardware connected to those lines is unusable without this: If the line is indeed active low, the generic GIC code will reject an irq spec with IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously disable the polarity inversion (writing 0 to the relevant bit) before unmasking the interrupt. Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature, just with a different number of external interrupt lines (and a different POR value for the INTPCR register). This driver should be prepared for supporting those by properly filling out the device tree node. I have the reference manuals for all three boards, but I've only tested the driver on an LS1021A. Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set. Signed-off-by: Rasmus Villemoes Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk

irqchip: Add irq-ingenic-tcu driver

2019-08-08T22:30:07Z

This driver handles the interrupt controller built in the Timer/Counter Unit (TCU) of the JZ47xx SoCs from Ingenic. Signed-off-by: Paul Cercueil Tested-by: Mathieu Malaterre Tested-by: Artur Rojek Reviewed-by: Thomas Gleixner Acked-by: Marc Zyngier Signed-off-by: Paul Burton Cc: Ralf Baechle Cc: James Hogan Cc: Jonathan Corbet Cc: Lee Jones Cc: Arnd Bergmann Cc: Daniel Lezcano Cc: Michael Turquette Cc: Stephen Boyd Cc: Jason Cooper Cc: Marc Zyngier Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-mips@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: od@zcrc.me

irqchip/al-fic: Introduce Amazon's Annapurna Labs Fabric Interrupt Controller Driver

2019-07-03T08:19:11Z

The Amazon's Annapurna Labs Fabric Interrupt Controller has 32 inputs. A FIC (Fabric Interrupt Controller) may be cascaded into another FIC or directly to the main CPU Interrupt Controller (e.g. GIC). Signed-off-by: Talel Shenhar Signed-off-by: Marc Zyngier

irqchip: Add Renesas RZ/A1 Interrupt Controller driver

2019-05-29T09:42:25Z

Add a driver for the Renesas RZ/A1 Interrupt Controller. This supports using up to 8 external interrupts on RZ/A1, with configurable sense select. NMI edge select is not yet supported. Signed-off-by: Geert Uytterhoeven Tested-by: Chris Brandt Reviewed-by: Simon Horman Signed-off-by: Marc Zyngier

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2019-05-19T17:58:45Z

Pull IRQ chip updates from Ingo Molnar: "A late irqchips update: - New TI INTR/INTA set of drivers - Rewrite of the stm32mp1-exti driver as a platform driver - Update the IOMMU MSI mapping API to be RT friendly - A number of cleanups and other low impact fixes" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) iommu/dma-iommu: Remove iommu_dma_map_msi_msg() irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg() irqchip/ls-scfg-msi: Don't map the MSI page in ls_scfg_msi_compose_msg() irqchip/gic-v3-its: Don't map the MSI page in its_irq_compose_msi_msg() irqchip/gicv2m: Don't map the MSI page in gicv2m_compose_msi_msg() iommu/dma-iommu: Split iommu_dma_map_msi_msg() in two parts genirq/msi: Add a new field in msi_desc to store an IOMMU cookie arm64: arch_k3: Enable interrupt controller drivers irqchip/ti-sci-inta: Add msi domain support soc: ti: Add MSI domain bus support for Interrupt Aggregator irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings irqchip/ti-sci-intr: Add support for Interrupt Router driver dt-bindings: irqchip: Introduce TISCI Interrupt router bindings gpio: thunderx: Use the default parent apis for {request,release}_resources genirq: Introduce irq_chip_{request,release}_resource_parent() apis firmware: ti_sci: Add helper apis to manage resources firmware: ti_sci: Add RM mapping table for am654 firmware: ti_sci: Add support for IRQ management firmware: ti_sci: Add support for RM core ops ...