wireguard-linux/drivers/media/platform/sunxi, branch jd/unified-crypt-queue

media: sun8i: Add Allwinner A83T Rotate driver

2020-03-02T14:16:40Z

Allwinner A83T contains rotation core which can rotate and flip images. Add a driver for it. Signed-off-by: Jernej Skrabec [hverkuil-cisco@xs4all.nl: MAINTAINERS paths were out of date, fix that] [hverkuil-cisco@xs4all.nl: VFL_TYPE_GRABBER -> _VIDEO] [hverkuil-cisco@xs4all.nl: Fix module build] Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

media: Split v4l2_pipeline_pm_use into v4l2_pipeline_pm_{get, put}

2020-03-02T14:11:40Z

Currently, v4l2_pipeline_pm_use() prototype is: int v4l2_pipeline_pm_use(struct media_entity *entity, int use) Where the 'use' argument shall only be set to '1' for enable/power-on, or to '0' for disable/power-off. The integer return is specified as only meaningful when 'use' is set to '1'. Let's enforce this semantic by splitting the function in two: v4l2_pipeline_pm_get and v4l2_pipeline_pm_put. This is done for several reasons. It makes the API easier to use (or harder to misuse). It removes the constraint on the values the 'use' argument shall take. Also, it removes the need to constraint the return value, by making v4l2_pipeline_pm_put void return. And last, it's more consistent with other kernel APIs, such as the runtime pm APIs, which makes the code more symmetric. Signed-off-by: Ezequiel Garcia Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

media: sun8i: Remove redundant platform_get_irq error message

2020-02-24T16:14:33Z

platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

media: media/platform: rename VFL_TYPE_GRABBER to _VIDEO

2020-02-24T15:54:14Z

'GRABBER' is a weird name, all other types map to the /dev device names. Rename to 'VIDEO' to be consistent with the other types. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

media: sun4i-csi: Add support for A10 CSI1 camera sensor interface

2020-01-04T07:21:35Z

The A10/A20 Allwinner SoCs have two camera sensor interface blocks, named CSI0 and CSI1. The two have the same register layouts with slightly different features: - CSI0 has an image signal processor (ISP); CSI1 doesn't - CSI0 can support up to four separate channels under CCIR656; CSI1 can only support one - CSI0 can support up to 16-bit wide bus with YUV422; CSI1 can support up to 24-bit wide bus with YUV444 For now the driver doesn't support wide busses, nor CCIR656. So the only relevant difference is whether a clock needs to be taken and enabled for the ISP. Add structs to record the differences, tie them to the compatible strings, and deal with the ISP clock. Support for the new CSI1 hardware block is added as well. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab

media: sun4i-csi: Deal with DRAM offset

2020-01-04T07:19:01Z

On Allwinner SoCs, some high memory bandwidth devices do DMA directly over the memory bus (called MBUS), instead of the system bus. These devices include the CSI camera sensor interface, video (codec) engine, display subsystem, etc.. The memory bus has a different addressing scheme without the DRAM starting offset. Deal with this using the "interconnects" property from the device tree, or if that is not available, set dev->dma_pfn_offset to PHYS_PFN_OFFSET. Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver") Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab

media: sun4i-csi: Fix [HV]sync polarity handling

2020-01-04T07:17:57Z

The Allwinner camera sensor interface has a different definition of [HV]sync. While the timing diagram uses the names HSYNC and VSYNC, the note following the diagram and register names use HREF and VREF. Combined they imply the hardware uses either [HV]REF or inverted [HV]SYNC. There are also registers to set horizontal skip lengths in pixels and vertical skip lengths in lines, also known as back porches. Fix the polarity handling by using the opposite polarity flag for the checks. Also rename `[hv]sync_pol` to `[hv]ref_pol` to better match the hardware register description. Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver") Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab

media: sun4i-csi: Fix data sampling polarity handling

2020-01-04T07:17:14Z

The CLK_POL field specifies whether data is sampled on the falling or rising edge of PCLK, not whether the data lines are active high or low. Evidence of this can be found in the timing diagram labeled "horizontal size setting and pixel clock timing". Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING. While at it, reorder the three polarity flag checks so HSYNC and VSYNC are grouped together. Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver") Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab

media: sun8i: Remove redundant dev_err call in deinterlace_probe()

2019-12-16T09:20:10Z

There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun Acked-by: Jernej Skrabec Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

media: sun4i: Add H3 deinterlace driver

2019-10-24T22:07:59Z

Allwinner H3 SoC contains deinterlace unit, which has several modes of operation - bypass, weave, bob and mixed (advanced) mode. I don't know how mixed mode works, but according to Allwinner it gives best results, so they use it exclusively. Currently this mode is also hardcoded here. For each interleaved frame queued, this driver produces 2 deinterlaced frames. Deinterlaced frames are based on 2 consequtive output buffers, except for the first 2, where same output buffer is given to peripheral as current and previous. There is no documentation for this core, so register layout and fixed values were taken from BSP driver. I'm not sure if maximum size of the image unit is capable to process is governed by size of "flag" buffers, frequency or it really is some HW limitation. Currently driver can process full HD image in ~15ms (7.5ms for each capture buffer), which allows to process 1920x1080@60i video smoothly in real time. Acked-by: Maxime Ripard Signed-off-by: Jernej Skrabec [hverkuil-cisco@xs4all.nl: add static to deinterlace_ioctl_ops] Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab