wireguard-linux/drivers/net/dsa/realtek, branch stable

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2026-08-18T17:42:41Z

Merge in late fixes in preparation for the net-next PR. Conflicts: drivers/dpll/dpll_core.c drivers/dpll/dpll_netlink.c 33f016b23a219 ("dpll: fix NULL deref in dpll_device_ops() during teardown race") b1d0c412088e3 ("dpll: add STATE_CONNECTED_OVERRIDE pin capability") https://lore.kernel.org/aoR9YYY2P5--3x0N@sirena.org.uk https://lore.kernel.org/aoR9VmKllVGwmQn_@sirena.org.uk No adjacent changes. Signed-off-by: Jakub Kicinski

net: dsa: realtek: use gpiod_set_value_cansleep for reset GPIO

2026-08-18T01:26:18Z

rtl83xx_reset_assert() and rtl83xx_reset_deassert() are only called from the probe path, which may sleep and is not timing-critical. When the reset GPIO is provided by a sleeping controller such as an I2C I/O expander, gpiod_set_value() warns: WARNING: drivers/gpio/gpiolib.c:4030 at gpiod_set_value+0x44/0x80, CPU#1: kworker/u16:4/61 Hardware name: B&O MAP CA33 Rev f (UNKNOWN) (DT) Workqueue: events_unbound deferred_probe_work_func pc : gpiod_set_value+0x44/0x80 lr : rtl83xx_probe+0x1d8/0x3a0 Call trace: gpiod_set_value+0x44/0x80 (P) rtl83xx_probe+0x1d8/0x3a0 realtek_mdio_probe+0x24/0xa0 mdio_probe+0x38/0x78 really_probe+0xc4/0x3e0 __driver_probe_device+0x15c/0x1b8 driver_probe_device+0xb4/0x120 __device_attach_driver+0xb8/0x1a0 bus_for_each_drv+0x88/0xf0 __device_attach+0xa0/0x1d8 device_initial_probe+0x54/0x68 bus_probe_device+0x38/0xa0 deferred_probe_work_func+0xb8/0x120 process_one_work+0x184/0x4e8 worker_thread+0x188/0x308 kthread+0x130/0x150 ret_from_fork+0x10/0x20 Switch both helpers to gpiod_set_value_cansleep() so such a reset GPIO can be used without triggering the warning. The reset GPIO has been driven with the non-sleeping gpiod_set_value() since the driver was added in v4.19. The call has since been refactored across several files - from realtek-smi.c / realtek-mdio.c into the common rtl83xx.c module and then into the rtl83xx_reset_assert() and rtl83xx_reset_deassert() helpers (both in v6.9). This patch therefore applies as-is only to kernels that carry those helpers (v6.9+); older stable kernels need the same gpiod_set_value_cansleep() conversion at the corresponding open-coded call sites. Fixes: d8652956cf37 ("net: dsa: realtek-smi: Add Realtek SMI driver") Cc: # 6.9.x Signed-off-by: Ahmad Fatoum Co-developed-by: Oleksij Rempel Signed-off-by: Oleksij Rempel Reviewed-by: Alvin Šipraga Reviewed-by: Linus Walleij Reviewed-by: Luiz Angelo Daros de Luca Link: https://patch.msgid.link/20260814110102.2362246-1-o.rempel@pengutronix.de Signed-off-by: Jakub Kicinski

net: dsa: realtek: rtl8366rb: Fix up port isolation

2026-08-05T00:00:53Z

Sashiko reports that we incorrectly disable isolation in the setup loop while what we want to do is to enable it. Enable it by unconditionally setting the enable bit 0 in rtl8366rb_port_set_isolation() so a mask of 0 when passed in will enable isolation and isolate from ALL ports. Fix up the comments so it is clear what is going on, including a missing word in the helper function. Reported-by: Paolo Abeni Closes: https://sashiko.dev/#/patchset/20260630-rtl8366rb-improvements-v2-0-05eb9d6a37f5%40kernel.org Signed-off-by: Linus Walleij Link: https://patch.msgid.link/20260731-rtl8366rb-fixes-v4-1-fbf0c95b829a@kernel.org Signed-off-by: Jakub Kicinski

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2026-07-30T19:53:19Z

Cross-merge networking fixes after downstream PR (net-7.2-rc6). No conflicts. Adjacent changes: net/ipv4/route.c dbc3791e3b24 ("net: do not send ICMP/NDISC Redirects when peer allocation fails") 7804eaa057fe ("ipv4: snapshot dst.dev in ip_rt_send_redirect() and ip_rt_get_source()") drivers/net/tun.c 23dad2d088df ("tun: no longer rely on RTNL in tun_fill_info()") c3da92af07ea ("Revert "tun/tap: add ptr_ring consume helper with netdev queue wakeup"") drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c 3bd438a58e91 ("octeontx2-af: Block VFs from clobbering special CGX PKIND state") 5ba5611ef946 ("octeontx2-af: reserve 4 PKINDs for skip-size custom use") drivers/net/wireless/ath/ath12k/core.h drivers/net/wireless/ath/ath12k/mac.c drivers/net/wireless/ath/ath12k/peer.c 469d7e6077c1 ("wifi: ath12k: resolve PENDING ML peer ID from MLO_PEER_MAP HTT event") 378e659029d5 ("wifi: ath12k: introduce host_alloc_ml_id hardware parameter") c42b27336eef ("wifi: ath12k: fix survey indexing across bands") Signed-off-by: Jakub Kicinski

net: dsa: realtek: use devm_mutex_init for l2_lock

2026-07-30T01:42:27Z

With CONFIG_DEBUG_MUTEXES enabled, mutex_destroy() needs to be called before the lock is discarded. Use devm_mutex_init() instead so the cleanup is handled automatically. Fixes: 336e3e4a1ab37 ("net: dsa: realtek: rtl8365mb: add FDB support") Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Linus Walleij Reviewed-by: Alvin Šipraga Link: https://patch.msgid.link/20260726-realtek_mutext-v2-4-5d62ba998791@gmail.com Signed-off-by: Jakub Kicinski

net: dsa: realtek: use devm_mutex_init for vlan_lock

2026-07-30T01:42:27Z

With CONFIG_DEBUG_MUTEXES enabled, mutex_destroy() needs to be called before the lock is discarded. Use devm_mutex_init() instead so the cleanup is handled automatically. Fixes: 9da2c8672f771 ("net: dsa: realtek: rtl8365mb: add VLAN support") Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Linus Walleij Reviewed-by: Alvin Šipraga Link: https://patch.msgid.link/20260726-realtek_mutext-v2-3-5d62ba998791@gmail.com Signed-off-by: Jakub Kicinski

net: dsa: realtek: use devm_mutex_init for regmap lock

2026-07-30T01:42:27Z

With CONFIG_DEBUG_MUTEXES enabled, mutex_destroy() needs to be called before the lock is discarded. Use devm_mutex_init() instead so the cleanup is handled automatically. Fixes: 907e772f6f6de ("net: dsa: realtek: allow subdrivers to externally lock regmap") Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Linus Walleij Reviewed-by: Alvin Šipraga Link: https://patch.msgid.link/20260726-realtek_mutext-v2-2-5d62ba998791@gmail.com Signed-off-by: Jakub Kicinski

net: dsa: realtek: rtl8365mb: use devm_mutex_init for mib_lock

2026-07-30T01:42:27Z

With CONFIG_DEBUG_MUTEXES enabled, mutex_destroy() needs to be called before the lock is discarded. Use devm_mutex_init() instead so the cleanup is handled automatically. Fixes: 4af2950c50c86 ("net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC") Reviewed-by: Mieczyslaw Nalewaj Signed-off-by: Luiz Angelo Daros de Luca Reviewed-by: Linus Walleij Reviewed-by: Alvin Šipraga Link: https://patch.msgid.link/20260726-realtek_mutext-v2-1-5d62ba998791@gmail.com Signed-off-by: Jakub Kicinski

net: dsa: realtek: rtl8365mb: add HSGMII support for RTL8367S

2026-07-22T16:37:29Z

In addition to SGMII, the RTL8367S SerDes also supports HSGMII, which carries 2.5 Gbps with the same signaling as SGMII at 2.5x clock rate. The chip info table already declares HSGMII as a supported interface mode for external interface 1. Extend the SerDes PCS to handle HSGMII, which phylink represents as 2500base-x: - Select the HSGMII SerDes tuning parameters and external interface mode, and mux the SerDes to MAC8 in HSGMII mode, from pcs_config() according to the interface. The parameters are again lifted from the GPL-licensed Realtek rtl8367c vendor driver, and again only cover the tuning variant for a non-zero chip option, so the mode is gated on the option probed at setup. - Advertise 2500base-x and MAC_2500FD on ports whose external interface supports HSGMII. - Accept SPEED_2500 in the forced link configuration. The MAC speed field has no 2.5 Gbps value: the rate is determined by the HSGMII SerDes configuration, and the vendor driver programs the 1 Gbps value here, so do the same. - Raise the port 6 ingress and egress rate limiters to their maximum at setup time, as the vendor switch init does unconditionally for the whole chip family. The chip resets them to 0x1FFFF (~1.048 Gbps in units of 8 Kbps), which caps the aggregate HSGMII throughput at roughly 1 Gbps. The vendor documentation describes the reset default as disabling the limiter, but the cap is real: on an RTL8367S-based Mercusys MR85X running an OpenWrt backport of this series, several clients on 1 Gbps user ports were limited to about 1.02 Gbps combined across the HSGMII CPU port until these limiters were raised, after which throughput reached about 2 Gbps [1]. The related HSGMII scheduler line rate (LINE_RATE_HSG_H) is already set to its maximum by the common init jam table. Tested on a Mercusys MR80X v2.20, where the RTL8367S is connected to the SoC over HSGMII. Link: https://github.com/openwrt/openwrt/pull/19445#issuecomment-4505613294 [1] Suggested-by: Luiz Angelo Daros de Luca Suggested-by: Mieczyslaw Nalewaj Signed-off-by: Johan Alvarado Tested-by: Stanisław Pal Reviewed-by: Luiz Angelo Daros de Luca Reviewed-by: Mieczyslaw Nalewaj Tested-by: Stanislaw Pal Link: https://patch.msgid.link/20260711-rtl8367s-sgmii-v6-2-88f7944ddca7@c127.dev Signed-off-by: Jakub Kicinski

net: dsa: realtek: rtl8365mb: add SGMII support for RTL8367S

2026-07-22T16:37:29Z

The RTL8367S can mux its embedded SerDes to external interface 1, which is typically used to connect the switch to a CPU port. The chip info table already declares SGMII as a supported interface mode for this chip, but the driver only implements RGMII so far. Implement SGMII support as a phylink PCS, with the configuration sequence derived from the GPL-licensed Realtek rtl8367c vendor driver as distributed in the Mercusys MR80X GPL code drop: - Add accessors for the SerDes indirect access registers (SDS_INDACS), through which the SerDes internal registers are reached. - Register a phylink_pcs for the SerDes, selected from mac_select_pcs for the SGMII interface, so the SerDes handling lives in the PCS operations rather than in the MAC operations. - Probe the SerDes tuning variant from the chip option register once at setup. The vendor driver keeps two sets of SerDes tuning parameters and selects between them based on this option; only the variant for a non-zero option (which all RTL8367S parts seen so far report) has been validated on hardware, so the SerDes interface modes are only advertised in that case. An unsupported variant thus fails at phylink validation time instead of at link configuration time. - Keep the embedded DW8051 microcontroller in reset and disabled. The vendor driver loads firmware into it to manage the SerDes link, but analysis of that firmware shows it only duplicates the link management phylink already performs: it polls the port status and writes the external interface force registers behind the driver's back. - Clear the line rate bypass bit for the external interface, tune the SerDes with the vendor-prescribed parameters, mux the SerDes to MAC8 in SGMII mode and only then take the SerDes out of reset, as the vendor driver does. - After deasserting the SerDes reset, reset the SerDes data path via the SerDes BMCR register to flush the FIFOs and resync the PLL. This mirrors what the vendor firmware does right after deasserting the SerDes reset, and ensures a clean link state from cold boot. - Force the SGMII link parameters (link, speed, duplex) in the SDS_MISC register from pcs_link_up(). SGMII in-band autonegotiation is not implemented, so only fixed-link and conventional PHY setups are supported, just like RGMII. This is reported to phylink through pcs_inband_caps() returning LINK_INBAND_DISABLE, so phylink never selects an in-band-enabled negotiation mode for this PCS. - Program the SerDes pause enables in SDS_MISC from the resolved pause modes when forcing the MAC external interface in mac_link_up, as the vendor driver does, rather than leaving whatever state the boot firmware left there. Flow control testing shows these bits, not the MAC force pause bits, gate pause on the SerDes external interface. This is done in the MAC layer because pcs_link_up() carries no pause information. - Implement pcs_get_state() by reading the link status from the SerDes, with the forced speed and duplex read back from SDS_MISC. Although the supported fixed-link and conventional PHY setups do not use it, the PCS owns the SerDes link state, and phylink consults pcs_get_state() to track the physical link when operating in in-band mode with autonegotiation disabled. The SerDes has no link interrupt wired up, so the PCS sets its poll flag. Tested on a Mercusys MR80X v2.20, where the RTL8367S is connected to the SoC over SGMII. Suggested-by: Luiz Angelo Daros de Luca Suggested-by: Maxime Chevallier Suggested-by: Mieczyslaw Nalewaj Signed-off-by: Johan Alvarado Reviewed-by: Maxime Chevallier Reviewed-by: Luiz Angelo Daros de Luca Reviewed-by: Mieczyslaw Nalewaj Tested-by: Stanislaw Pal Link: https://patch.msgid.link/20260711-rtl8367s-sgmii-v6-1-88f7944ddca7@c127.dev Signed-off-by: Jakub Kicinski