<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/net/ethernet/sfc/tx.c, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/net/ethernet/sfc/tx.c?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/net/ethernet/sfc/tx.c?h=jd%2Forphan-parallel'/>
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<updated>2020-09-12T00:15:22Z</updated>
<entry>
<title>sfc: de-indirect TSO handling</title>
<updated>2020-09-12T00:15:22Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-11T22:40:03Z</published>
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<id>urn:sha1:1679c72cf48552e75a624b9c9230e2c7c18cfffc</id>
<content type='text'>
Remove the tx_queue-&gt;handle_tso function pointer, and just use
 tx_queue-&gt;tso_version to decide which function to call, thus removing
 an indirect call from the fast path.
Instead of passing a tso_v2 flag to efx_mcdi_tx_init(), set the desired
 tx_queue-&gt;tso_version before calling it.
In efx_mcdi_tx_init(), report back failure to obtain a TSOv2 context by
 setting tx_queue-&gt;tso_version to 0, which will cause the TX path to
 use the GSO-based fallback.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: select inner-csum-offload TX queues for skbs that need it</title>
<updated>2020-09-12T00:15:22Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-11T22:39:39Z</published>
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<id>urn:sha1:fe0c4060c1b90fabfcab387dc374edde420a98d6</id>
<content type='text'>
Won't actually be exercised until we start advertising the corresponding
 offload features.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: define inner/outer csum offload TXQ types</title>
<updated>2020-09-12T00:15:22Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-11T22:39:14Z</published>
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<id>urn:sha1:044588b9637277b0b15f295a814bdc282113f3c4</id>
<content type='text'>
Nothing yet creates inner csum TXQs; just change all references to
 EFX_TXQ_TYPE_OFFLOAD to the new EFX_TXQ_TYPE_OUTER_CSUM.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: decouple TXQ type from label</title>
<updated>2020-09-12T00:15:22Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-11T22:39:02Z</published>
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<id>urn:sha1:12804793b17c0e19115a90d98f2f3df0cb79e233</id>
<content type='text'>
Make it possible to have an arbitrary mapping from types to labels,
 because when we add inner-csum-offload TXQs there will no longer be a
 convenient nesting hierarchy of NIC types (EF10 will have inner-csum
 TXQs, while Siena will have HIGHPRI).
Correct a misleading comment on efx_hard_start_xmit().

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: rewrite efx_tx_may_pio</title>
<updated>2020-09-05T19:21:40Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-03T21:35:29Z</published>
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<id>urn:sha1:8be41842c5303726d55240e16b9340311ad7cacd</id>
<content type='text'>
Use efx_for_each_channel_tx_queue() rather than efx_tx_queue_partner().
Make some related simplifications of efx_nic_tx_is_empty() to remove
 entry points that aren't used.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>sfc: use efx_channel_tx_[old_]fill_level() in Siena/EF10 TX datapath</title>
<updated>2020-09-05T19:21:40Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-03T21:35:13Z</published>
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<id>urn:sha1:0d8c122907d96448495700fa2c6229ab519f3252</id>
<content type='text'>
Instead of open-coding the calculation with efx_tx_queue_partner(), use
 the functions that iterate over numbers of queues other than 2 with
 efx_for_each_channel_tx_queue().

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>sfc: add and use efx_tx_send_pending in tx.c</title>
<updated>2020-09-05T19:21:39Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-09-03T21:34:15Z</published>
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<id>urn:sha1:1c0544d24927e4fad04f858216b8ea767a3bd123</id>
<content type='text'>
Instead of using efx_tx_queue_partner(), which relies on the assumption
 that tx_queues_per_channel is 2, efx_tx_send_pending() iterates over
 txqs with efx_for_each_channel_tx_queue().
We unconditionally set tx_queue-&gt;xmit_pending (renamed from
 xmit_more_available), then condition on xmit_more for the call to
 efx_tx_send_pending(), which will clear xmit_pending.  Thus, after an
 xmit_more TX, the doorbell is un-rung and xmit_pending is true.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>sfc: skeleton EF100 PF driver</title>
<updated>2020-07-27T19:26:55Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-27T11:55:55Z</published>
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<id>urn:sha1:51b35a454efdcd86f578e61ec8bf7596299c5f80</id>
<content type='text'>
No TX or RX path, no MCDI, not even an ifup/down handler.
Besides stubs, the bulk of the patch deals with reading the Xilinx
 extended PCIe capability, which tells us where to find our BAR.

Though in the same module, EF100 has its own struct pci_driver,
 which is named sfc_ef100.

A small number of additional nic_type methods are added; those in the
 TX (tx_enqueue) and RX (rx_packet) paths are called through indirect
 call wrappers to minimise the performance impact.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: assign TXQs without gaps</title>
<updated>2020-07-02T21:47:40Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-02T16:29:58Z</published>
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<id>urn:sha1:a81dcd85a7c1bc548ce8fb635623970fdee5887d</id>
<content type='text'>
Since we only allocate VIs for the number of TXQs we actually need, we
 cannot naively use "channel * TXQ_TYPES + txq" for the TXQ number, as
 this has gaps (when efx-&gt;tx_queues_per_channel &lt; EFX_TXQ_TYPES) and
 thus overruns the driver's VI allocations, causing the firmware to
 reject the MC_CMD_INIT_TXQ based on INSTANCE.
Thus, we distinguish INSTANCE (stored in tx_queue-&gt;queue) from LABEL
 (tx_queue-&gt;label); the former is allocated starting from 0 in
 efx_set_channels(), while the latter is simply the txq type (index in
 channel-&gt;tx_queue array).
To simplify things, rather than changing tx_queues_per_channel after
 setting up TXQs, make Siena always probe its HIGHPRI queues at start
 of day, rather than deferring it until tc mqprio enables them.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>sfc: make tx_queues_per_channel variable at runtime</title>
<updated>2020-07-02T21:47:40Z</updated>
<author>
<name>Edward Cree</name>
<email>ecree@solarflare.com</email>
</author>
<published>2020-07-02T16:29:24Z</published>
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<id>urn:sha1:f9cac93e5b3eefc5c6340ba4efd3628f2347e1ef</id>
<content type='text'>
Siena needs four TX queues (csum * highpri), EF10 needs two (csum),
 and EF100 only needs one (as checksumming is controlled entirely by
 the transmit descriptor).  Rather than having various bits of ad-hoc
 code to decide which queues to set up etc., put the knowledge of how
 many TXQs a channel has in one place.

Signed-off-by: Edward Cree &lt;ecree@solarflare.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
</feed>
