<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/pci/controller/dwc, branch jd/bump-compilers</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/pci/controller/dwc?h=jd%2Fbump-compilers</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/pci/controller/dwc?h=jd%2Fbump-compilers'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2024-08-21T21:31:41Z</updated>
<entry>
<title>PCI: qcom: Use OPP only if the platform supports it</title>
<updated>2024-08-21T21:31:41Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2024-07-22T13:11:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=db1ec60fba4a995975dc1dc837b408db0d666801'/>
<id>urn:sha1:db1ec60fba4a995975dc1dc837b408db0d666801</id>
<content type='text'>
With commit 5b6272e0efd5 ("PCI: qcom: Add OPP support to scale
performance"), OPP was used to control the interconnect and power domains
if the platform supported OPP. Also to maintain the backward compatibility
with platforms not supporting OPP but just ICC, the above mentioned commit
assumed that if ICC was not available on the platform, it would resort to
OPP.

Unfortunately, some old platforms don't support either ICC or OPP. On those
platforms, resorting to OPP in the absence of ICC throws below errors from
OPP core during suspend and resume:

  qcom-pcie 1c08000.pcie: dev_pm_opp_set_opp: device opp doesn't exist
  qcom-pcie 1c08000.pcie: _find_key: OPP table not found (-19)

Also, it doesn't make sense to invoke the OPP APIs when OPP is not
supported by the platform at all.

Add a "use_pm_opp" flag to identify whether OPP is supported and use it to
control invoking the OPP APIs.

Fixes: 5b6272e0efd5 ("PCI: qcom: Add OPP support to scale performance")
Link: https://lore.kernel.org/linux-pci/20240722131128.32470-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Reviewed-by: Mayank Rana &lt;quic_mrana@quicinc.com&gt;
</content>
</entry>
<entry>
<title>PCI: qcom-ep: Disable MHI RAM data parity error interrupt for SA8775P SoC</title>
<updated>2024-08-21T21:30:42Z</updated>
<author>
<name>Manivannan Sadhasivam</name>
<email>manivannan.sadhasivam@linaro.org</email>
</author>
<published>2024-08-08T06:30:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5d6a6c7454ebaefba518e334750b05700131923b'/>
<id>urn:sha1:5d6a6c7454ebaefba518e334750b05700131923b</id>
<content type='text'>
SA8775P SoC has support for the hardware parity check feature on the MHI
RAM (entity that holds MHI registers, etc.) But due to a hardware bug in
the parity check logic, the data parity error interrupt is getting
generated all the time when using MHI. So the hardware team has suggested
disabling the parity check error to work around the hardware bug.

Mask the parity error interrupt in PARF_INT_ALL_5_MASK register.

Fixes: 58d0d3e032b3 ("PCI: qcom-ep: Add support for SA8775P SOC")
Link: https://lore.kernel.org/linux-pci/20240808063057.7394-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Krzysztof Wilczyński &lt;kwilczynski@kernel.org&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'pci/misc'</title>
<updated>2024-07-19T15:10:33Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=45659274e60864f9acabba844468e405362bdc8c'/>
<id>urn:sha1:45659274e60864f9acabba844468e405362bdc8c</id>
<content type='text'>
- Remove unused struct 'acpi_handle_node' (Dr. David Alan Gilbert)

- Use array notation for portdrv .id_table consistently (Masahiro Yamada)

- Switch to new Intel CPU model defines (Tony Luck)

- Add missing MODULE_DESCRIPTION() macros (Jeff Johnson)

* pci/misc:
  PCI: controller: Add missing MODULE_DESCRIPTION() macros
  PCI: Add missing MODULE_DESCRIPTION() macros
  PCI/PM: Switch to new Intel CPU model defines
  PCI: Use array for .id_table consistently
  ACPI: PCI: Remove unused struct 'acpi_handle_node'
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/tegra194'</title>
<updated>2024-07-19T15:10:32Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=99329ded09099b40f755893b466571395d09ce46'/>
<id>urn:sha1:99329ded09099b40f755893b466571395d09ce46</id>
<content type='text'>
- Ensure Tegra194 and Tegra234 inbound ATU entries are 64KB-aligned to
  match the hardware restriction (Jon Hunter)

- Remove unused struct 'tegra_pcie_soc' (Dr. David Alan Gilbert)

* pci/controller/tegra194:
  PCI: tegra: Remove unused struct 'tegra_pcie_soc'
  PCI: tegra194: Set EP alignment restriction for inbound ATU
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/rockchip'</title>
<updated>2024-07-19T15:10:32Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9'/>
<id>urn:sha1:8240a9b4a5a27ce20a0ae2dea2b2e830be34f3b9</id>
<content type='text'>
- Use dev_err_probe() in dw-rockchip probe error path so the failures
  aren't silent (Uwe Kleine-König)

- Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal)

- Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a
  config access (Damien Le Moal)

- Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value,
  which avoids a spurious PERST# assertion and fixes a Qcom modem firmware
  crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan
  Sadhasivam for rockchip, Niklas Cassel for dw-rockchip)

- Refactor dw-rockchip and add support for Endpoint mode for rk3568 and
  rk3588 (Niklas Cassel)

* pci/controller/rockchip:
  PCI: dw-rockchip: Use pci_epc_init_notify() directly
  PCI: dw-rockchip: Add endpoint mode support
  PCI: dw-rockchip: Refactor the driver to prepare for EP mode
  PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
  PCI: dw-rockchip: Fix weird indentation
  PCI: dw-rockchip: Fix initial PERST# GPIO value
  PCI: dw-rockchip: Add error messages in .probe() error paths
  PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio
  PCI: rockchip-host: Wait 100ms after reset before starting configuration
  PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/rcar-gen4'</title>
<updated>2024-07-19T15:10:31Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=59dd7046b4fbe60d74544f8a77c63899ce8b3618'/>
<id>urn:sha1:59dd7046b4fbe60d74544f8a77c63899ce8b3618</id>
<content type='text'>
- Add Synopsys DWC macros for lane skew configuration (Yoshihiro Shimoda)

- Add struct rcar_gen4_pcie_drvdata to provide for future SoCs with
  different initialization requirements (Yoshihiro Shimoda)

- Add .ltssm_control() method for SoC dependencies (Yoshihiro Shimoda)

- Add r8a779g0 (R-Car V4H) support (Yoshihiro Shimoda)

* pci/controller/rcar-gen4:
  PCI: rcar-gen4: Add support for R-Car V4H
  PCI: rcar-gen4: Add .ltssm_control() for other SoC support
  PCI: rcar-gen4: Add struct rcar_gen4_pcie_drvdata
  PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/qcom'</title>
<updated>2024-07-19T15:10:31Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=df5dd337283ad104ef329124d683b63d6b4dcd48'/>
<id>urn:sha1:df5dd337283ad104ef329124d683b63d6b4dcd48</id>
<content type='text'>
- Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid
  writing out all the clock names (Manivannan Sadhasivam)

- Add DT binding and driver support for the SA8775P SoC (Mrinmay Sarkar)

- Refactor dw_pcie_edma_find_chip() to enable adding support for Hyper DMA
  (HDMA) (Manivannan Sadhasivam)

- Enable drivers to supply the eDMA channel count since some can't auto
  detect this (Manivannan Sadhasivam)

- Add HDMA support for the SA8775P SoC (Mrinmay Sarkar)

- Override the SA8775P NO_SNOOP default to avoid possible memory corruption
  (Mrinmay Sarkar)

- Make sure resources are disabled during PERST# assertion, even if the
  link is already disabled (Manivannan Sadhasivam)

- Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays active
  even if other drivers don't vote for it (Krishna chaitanya chundru)

- Add Operating Performance Points (OPP) to scale performance state based
  on aggregate link bandwidth to improve SoC power efficiency (Krishna
  chaitanya chundru)

- Return failure instead of success if dev_pm_opp_find_freq_floor() fails
  (Dan Carpenter)

- Avoid an error pointer dereference if dev_pm_opp_find_freq_exact() fails
  (Dan Carpenter)

- Prevent use of uninitialized data in qcom_pcie_suspend_noirq() (Dan
  Carpenter)

* pci/controller/qcom:
  PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq()
  PCI: qcom: Prevent potential error pointer dereference
  PCI: qcom: Fix missing error code in qcom_pcie_probe()
  PCI: qcom: Add OPP support to scale performance
  PCI: Bring the PCIe speed to MBps logic to new pcie_dev_speed_mbps()
  PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path
  PCI: qcom-ep: Disable resources unconditionally during PERST# assert
  PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP
  PCI: qcom: Override NO_SNOOP attribute for SA8775P RC
  PCI: epf-mhi: Enable HDMA for SA8775P SoC
  PCI: qcom-ep: Add HDMA support for SA8775P SoC
  PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers
  PCI: dwc: Skip finding eDMA channels count for HDMA platforms
  PCI: dwc: Refactor dw_pcie_edma_find_chip() API
  PCI: qcom-ep: Add support for SA8775P SOC
  dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC
  PCI: qcom: Use devm_clk_bulk_get_all() API
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/keystone'</title>
<updated>2024-07-19T15:10:28Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=db2cc94fae135e2ea9d2de68c7a2b30a2fc75e74'/>
<id>urn:sha1:db2cc94fae135e2ea9d2de68c7a2b30a2fc75e74</id>
<content type='text'>
- Enable BAR 0 only for v3.65a to avoid Completion Timeouts that
  cause a 45 second boot delay on the v4.90a-based AM654x SoC (Siddharth
  Vadapalli)

- Avoid a NULL pointer dereference if DT failed to provide a host bridge
  memory window (Aleksandr Mishin)

* pci/controller/keystone:
  PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
  PCI: keystone: Fix NULL pointer dereference in case of DT error in ks_pcie_setup_rc_app_regs()
  PCI: keystone: Don't enable BAR 0 for AM654x
  PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/exynos'</title>
<updated>2024-07-19T15:10:27Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=da3552d2256c8bb8953a65d94b26994e29998f89'/>
<id>urn:sha1:da3552d2256c8bb8953a65d94b26994e29998f89</id>
<content type='text'>
- Use devm_clk_bulk_get_all_enable() to simplify clock setup (Shradha Todi)

* pci/controller/exynos:
  PCI: exynos: Adapt to use bulk clock APIs
</content>
</entry>
<entry>
<title>Merge branch 'pci/controller/dra7xx'</title>
<updated>2024-07-19T15:10:27Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2024-07-19T15:10:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=1d97f4b215396f3501732ff09f311494db3fbdec'/>
<id>urn:sha1:1d97f4b215396f3501732ff09f311494db3fbdec</id>
<content type='text'>
- Correct the dra7xx_pcie_cpu_addr_fixup() parameter name, which takes a
  CPU address but called it "pci_addr" (Niklas Cassel)

* pci/controller/dra7xx:
  PCI: dra7xx: Fix dra7xx_pcie_cpu_addr_fixup() parameter name
</content>
</entry>
</feed>
