<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/pci/controller/dwc, branch jd/orphan-parallel</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/pci/controller/dwc?h=jd%2Forphan-parallel</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/pci/controller/dwc?h=jd%2Forphan-parallel'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-10-21T14:58:43Z</updated>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/tegra'</title>
<updated>2020-10-21T14:58:43Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-10-21T14:58:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=214b2e042fbae7945cea46d8daaa54eac7b1a055'/>
<id>urn:sha1:214b2e042fbae7945cea46d8daaa54eac7b1a055</id>
<content type='text'>
- Drop return value checking for debugfs_create() calls (Greg
  Kroah-Hartman)

- Convert debugfs "ports" file to use DEFINE_SEQ_ATTRIBUTE() (Liu Shixin)

* remotes/lorenzo/pci/tegra:
  PCI: tegra: Convert to use DEFINE_SEQ_ATTRIBUTE macro
  PCI: tegra: No need to check return value of debugfs_create() functions
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/qcom'</title>
<updated>2020-10-21T14:58:43Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-10-21T14:58:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=3b353982202be8ac36aab1636c365e02f8dd46a0'/>
<id>urn:sha1:3b353982202be8ac36aab1636c365e02f8dd46a0</id>
<content type='text'>
- Make sure PCIe is reset before init to work around QSDK U-Boot issue
  (Ansuel Smith)

- Set iproc affinity mask on MSI interrupts (Mark Tomlinson)

* remotes/lorenzo/pci/qcom:
  PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/meson'</title>
<updated>2020-10-21T14:58:41Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-10-21T14:58:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=92f27db7b1bdc9611425e74fbd101c88ab21269e'/>
<id>urn:sha1:92f27db7b1bdc9611425e74fbd101c88ab21269e</id>
<content type='text'>
- Add pci-meson module support and enable by default on ARCH_MESON (Kevin
  Hilman)

* remotes/lorenzo/pci/meson:
  PCI: meson: Build as module by default
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/kirin'</title>
<updated>2020-10-21T14:58:41Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-10-21T14:58:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=29828fc20ab1c5d2f41e2749921c4bd32da6c38e'/>
<id>urn:sha1:29828fc20ab1c5d2f41e2749921c4bd32da6c38e</id>
<content type='text'>
- Return -EPROBE_DEFER in case the gpio isn't ready (Bean Huo)

* remotes/lorenzo/pci/kirin:
  PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't ready
</content>
</entry>
<entry>
<title>Merge branch 'remotes/lorenzo/pci/imx6'</title>
<updated>2020-10-21T14:58:40Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2020-10-21T14:58:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=982f8334262d02bfcd41612411c7d8ff40011914'/>
<id>urn:sha1:982f8334262d02bfcd41612411c7d8ff40011914</id>
<content type='text'>
- Use "fallthrough" pseudo-keyword (Gustavo A. R. Silva)

- Drop redundant error messages after devm_clk_get() (Anson Huang)

* remotes/lorenzo/pci/imx6:
  PCI: imx6: Do not output error message when devm_clk_get() failed with -EPROBE_DEFER
  PCI: imx6: Use fallthrough pseudo-keyword
</content>
</entry>
<entry>
<title>PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()</title>
<updated>2020-10-20T10:14:24Z</updated>
<author>
<name>Hou Zhiqiang</name>
<email>Zhiqiang.Hou@nxp.com</email>
</author>
<published>2020-09-16T05:41:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=15b23906347c0af8778d1d4edeea415290342d35'/>
<id>urn:sha1:15b23906347c0af8778d1d4edeea415290342d35</id>
<content type='text'>
NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either
programmed or statically configured to forward the error triggered by a
link-down state (eg no connected endpoint device) on the system bus for
PCI configuration transactions; these errors are reported as an SError
at system level, which is fatal.

Enumerating a PCI tree when the PCIe link is down is not sensible
either, so even if the link-up check is racy (link can go down after
map_bus() is called) add a link-up check in map_bus() to prevent issuing
configuration transactions when the link is down.

SError report:

 SError Interrupt on CPU2, code 0xbf000002 -- SError
 CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67
 Hardware name: LS1046A RDB Board (DT)
 pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--)
 pc : pci_generic_config_read+0x3c/0xe0
 lr : pci_generic_config_read+0x24/0xe0
 sp : ffff80001003b7b0
 x29: ffff80001003b7b0 x28: ffff80001003ba74
 x27: ffff000971d96800 x26: ffff00096e77e0a8
 x25: ffff80001003b874 x24: ffff80001003b924
 x23: 0000000000000004 x22: 0000000000000000
 x21: 0000000000000000 x20: ffff80001003b874
 x19: 0000000000000004 x18: ffffffffffffffff
 x17: 00000000000000c0 x16: fffffe0025981840
 x15: ffffb94c75b69948 x14: 62203a383634203a
 x13: 666e6f635f726568 x12: 202c31203d207265
 x11: 626d756e3e2d7375 x10: 656877202c307830
 x9 : 203d206e66766564 x8 : 0000000000000908
 x7 : 0000000000000908 x6 : ffff800010900000
 x5 : ffff00096e77e080 x4 : 0000000000000000
 x3 : 0000000000000003 x2 : 84fa3440ff7e7000
 x1 : 0000000000000000 x0 : ffff800010034000
 Kernel panic - not syncing: Asynchronous SError Interrupt
 CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67
 Hardware name: LS1046A RDB Board (DT)
 Call trace:
  dump_backtrace+0x0/0x1c0
  show_stack+0x18/0x28
  dump_stack+0xd8/0x134
  panic+0x180/0x398
  add_taint+0x0/0xb0
  arm64_serror_panic+0x78/0x88
  do_serror+0x68/0x180
  el1_error+0x84/0x100
  pci_generic_config_read+0x3c/0xe0
  dw_pcie_rd_other_conf+0x78/0x110
  pci_bus_read_config_dword+0x88/0xe8
  pci_bus_generic_read_dev_vendor_id+0x30/0x1b0
  pci_bus_read_dev_vendor_id+0x4c/0x78
  pci_scan_single_device+0x80/0x100

Link: https://lore.kernel.org/r/20200916054130.8685-1-Zhiqiang.Hou@nxp.com
Signed-off-by: Hou Zhiqiang &lt;Zhiqiang.Hou@nxp.com&gt;
[lorenzo.pieralisi@arm.com: rewrote the commit log, remove Fixes tag]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: dwc: Fix MSI page leakage in suspend/resume</title>
<updated>2020-10-13T08:52:49Z</updated>
<author>
<name>Jisheng Zhang</name>
<email>Jisheng.Zhang@synaptics.com</email>
</author>
<published>2020-10-09T07:55:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=07940c369a6bf940ec4a00eeb76bf51daa4f3973'/>
<id>urn:sha1:07940c369a6bf940ec4a00eeb76bf51daa4f3973</id>
<content type='text'>
Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during suspend-to-RAM, so when we resume, we want to
redo the latter but not the former. If designware based driver (for
example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the
msi page will be leaked.

As pointed out by Rob and Ard, there's no need to allocate a page for
the MSI address, we could use an address in the driver data.

To avoid map the MSI msg again during resume, we move the map MSI msg
from dw_pcie_msi_init() to dw_pcie_host_init().

Suggested-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20201009155505.5a580ef5@xhacker.debian
Signed-off-by: Jisheng Zhang &lt;Jisheng.Zhang@synaptics.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled</title>
<updated>2020-10-13T08:52:49Z</updated>
<author>
<name>Jisheng Zhang</name>
<email>Jisheng.Zhang@synaptics.com</email>
</author>
<published>2020-10-09T07:54:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=742833249198bfd07944158eca50f740faf823f3'/>
<id>urn:sha1:742833249198bfd07944158eca50f740faf823f3</id>
<content type='text'>
If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK
and PCIE_MSI_INTR0_ENABLE registers.

Link: https://lore.kernel.org/r/20201009155436.27e67238@xhacker.debian
Signed-off-by: Jisheng Zhang &lt;Jisheng.Zhang@synaptics.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Gustavo Pimentel &lt;gustavo.pimentel@synopsys.com&gt;
</content>
</entry>
<entry>
<title>PCI: keystone: Remove iATU register mapping</title>
<updated>2020-10-13T08:52:49Z</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2020-09-30T05:36:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=b101a39897d8369366e8a901666a32ee6db3974d'/>
<id>urn:sha1:b101a39897d8369366e8a901666a32ee6db3974d</id>
<content type='text'>
After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.

Suggested-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/1601444167-11316-5-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Jingoo Han &lt;jingoohan1@gmail.com&gt;
Cc: Gustavo Pimentel &lt;gustavo.pimentel@synopsys.com&gt;
</content>
</entry>
<entry>
<title>PCI: dwc: Add common iATU register support</title>
<updated>2020-10-13T08:52:49Z</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2020-09-30T05:36:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=13ab639ed48c1e777682d1a80097594d21a193dc'/>
<id>urn:sha1:13ab639ed48c1e777682d1a80097594d21a193dc</id>
<content type='text'>
This gets iATU register area from reg property that has reg-names "atu".
In Synopsys DWC version 4.80 or later, since iATU register area is
separated from core register area, this area is necessary to get from
DT independently.

Suggested-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/1601444167-11316-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Cc: Murali Karicheri &lt;m-karicheri2@ti.com&gt;
Cc: Jingoo Han &lt;jingoohan1@gmail.com&gt;
Cc: Gustavo Pimentel &lt;gustavo.pimentel@synopsys.com&gt;
</content>
</entry>
</feed>
