<feed xmlns='http://www.w3.org/2005/Atom'>
<title>wireguard-linux/drivers/pci/endpoint, branch jd/unified-crypt-queue</title>
<subtitle>WireGuard for the Linux kernel</subtitle>
<id>https://git.zx2c4.com/wireguard-linux/atom/drivers/pci/endpoint?h=jd%2Funified-crypt-queue</id>
<link rel='self' href='https://git.zx2c4.com/wireguard-linux/atom/drivers/pci/endpoint?h=jd%2Funified-crypt-queue'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/'/>
<updated>2020-04-02T16:57:10Z</updated>
<entry>
<title>PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address</title>
<updated>2020-04-02T16:57:10Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-02-25T08:17:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=6f5e193bfb55963ce5f4f68cc927f371ddb0913b'/>
<id>urn:sha1:6f5e193bfb55963ce5f4f68cc927f371ddb0913b</id>
<content type='text'>
commit beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler"),
in order to raise MSI-X interrupt, obtained MSIX table address from
Base Address Register (BAR). However BAR only holds PCI address
programmed by the host whereas the MSI-X table should be in the local
memory.

Store the MSI-X table address (virtual address) as part of -&gt;set_bar()
callback and use that to get the message address and message data
here.

Fixes: beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler")
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Fix -&gt;set_msix() to take BIR and offset as arguments</title>
<updated>2020-04-02T16:57:10Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-02-25T08:17:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=83153d9f36e24978c6211d246cb6f532bf54e5dc'/>
<id>urn:sha1:83153d9f36e24978c6211d246cb6f532bf54e5dc</id>
<content type='text'>
commit 8963106eabdc ("PCI: endpoint: Add MSI-X interfaces") while
adding support to raise MSI-X interrupts from endpoint didn't include
BAR Indicator register (BIR) configuration and MSI-X table offset as
arguments in pci_epc_set_msix(). This would result in endpoint
controller register using random BAR indicator register, the memory
for which might not be allocated by the endpoint function driver.
Add BAR indicator register and MSI-X table offset as arguments in
pci_epc_set_msix() and allocate space for MSI-X table and pending
bit array (PBA) in pci-epf-test endpoint function driver.

Fixes: 8963106eabdc ("PCI: endpoint: Add MSI-X interfaces")
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: functions/pci-epf-test: Print throughput information</title>
<updated>2020-04-02T16:57:10Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-03-16T11:24:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5893c2e5353bb9a723d862d8b6ba8028a8f6a6eb'/>
<id>urn:sha1:5893c2e5353bb9a723d862d8b6ba8028a8f6a6eb</id>
<content type='text'>
Print throughput information in KB/s after every completed transfer,
including information on whether DMA is used or not.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Tested-by: Alan Mikhak &lt;alan.mikhak@sifive.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: functions/pci-epf-test: Add DMA support to transfer data</title>
<updated>2020-04-02T16:57:01Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-03-16T11:24:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5ebf3fc59bd20d17df3ba26159787d13cf20d362'/>
<id>urn:sha1:5ebf3fc59bd20d17df3ba26159787d13cf20d362</id>
<content type='text'>
Use dmaengine API and add support for transferring data using DMA.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Tested-by: Alan Mikhak &lt;alan.mikhak@sifive.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Fix clearing start entry in configfs</title>
<updated>2020-03-31T08:13:27Z</updated>
<author>
<name>Kunihiko Hayashi</name>
<email>hayashi.kunihiko@socionext.com</email>
</author>
<published>2020-02-26T05:52:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=f58d5f53c89479c12ad719c1960176442add5aaa'/>
<id>urn:sha1:f58d5f53c89479c12ad719c1960176442add5aaa</id>
<content type='text'>
After an endpoint is started through configfs, if 0 is written to the
configfs entry 'start', the controller stops but the epc_group-&gt;start
value remains 1.

A subsequent unlinking of the function from the controller would trigger
a spurious WARN_ON_ONCE() in pci_epc_epf_unlink() despite right
behavior.

Fix it by setting epc_group-&gt;start = 0 when a controller is stopped
using configfs.

Fixes: d74679911610 ("PCI: endpoint: Introduce configfs entry for configuring EP functions")
Signed-off-by: Kunihiko Hayashi &lt;hayashi.kunihiko@socionext.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Cc: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>PCI: pci-epf-test: Add support to defer core initialization</title>
<updated>2020-02-26T09:58:41Z</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2020-02-17T12:10:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=5e50ee27d4a52a817ab152128c48690ec7c5cdf1'/>
<id>urn:sha1:5e50ee27d4a52a817ab152128c48690ec7c5cdf1</id>
<content type='text'>
Add support to defer core initialization for the endpoint mode of
operation.

This would enable support for implementations where the core
initialization needs to be deferred until the PCIe reference clock is
available from the host system.

Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Add notification for core init completion</title>
<updated>2020-02-25T12:02:25Z</updated>
<author>
<name>Vidya Sagar</name>
<email>vidyas@nvidia.com</email>
</author>
<published>2020-02-17T12:10:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=0ef22dcf0c1871888c4c0ee46a9d9c494f2fe997'/>
<id>urn:sha1:0ef22dcf0c1871888c4c0ee46a9d9c494f2fe997</id>
<content type='text'>
Add support to send notifications to EPF from EPC once the core
registers initialization is complete.

Signed-off-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Assign function number for each PF in EPC core</title>
<updated>2020-02-24T10:15:45Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-02-24T09:53:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=2499ee84e02774a8573b7b4c76c8f2ea38669313'/>
<id>urn:sha1:2499ee84e02774a8573b7b4c76c8f2ea38669313</id>
<content type='text'>
The PCIe endpoint core relies on the drivers that invoke the
pci_epc_add_epf() API to allocate and assign a function number
to each physical function (PF). Since endpoint function device can
be created by multiple mechanisms (configfs, devicetree, etc..),
allowing each of these mechanisms to assign a function number
would result in mutliple endpoint function devices having the
same function number. In order to avoid this, let EPC core assign
a function number to the endpoint device.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex</title>
<updated>2020-02-24T10:15:33Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-02-24T09:53:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=07301c982643a432212840a4b648b5d3f5a061fa'/>
<id>urn:sha1:07301c982643a432212840a4b648b5d3f5a061fa</id>
<content type='text'>
Protect concurrent access to pci_epf_ops with a mutex.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: endpoint: Fix for concurrent memory allocation in OB address region</title>
<updated>2020-02-24T10:13:48Z</updated>
<author>
<name>Kishon Vijay Abraham I</name>
<email>kishon@ti.com</email>
</author>
<published>2020-02-24T09:53:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/wireguard-linux/commit/?id=04e046ca57ebed3943422dee10eec9e73aec081e'/>
<id>urn:sha1:04e046ca57ebed3943422dee10eec9e73aec081e</id>
<content type='text'>
pci-epc-mem uses a bitmap to manage the Endpoint outbound (OB) address
region. This address region will be shared by multiple endpoint
functions (in the case of multi function endpoint) and it has to be
protected from concurrent access to avoid updating an inconsistent state.

Use a mutex to protect bitmap updates to prevent the memory
allocation API from returning incorrect addresses.

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Cc: stable@vger.kernel.org # v4.14+
</content>
</entry>
</feed>
