wireguard-linux/drivers/phy/cadence, branch jd/orphan-parallelWireGuard for the Linux kernelhttps://git.zx2c4.com/wireguard-linux/atom/drivers/phy/cadence?h=jd%2Forphan-parallel2020-09-18T05:17:22Zphy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration2020-09-18T05:17:22ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:46Zurn:sha1:6fd428f7806000d4be141f2ab4b08e2c5e998f05
Add USB + SGMII/QSGMII multilink configuration sequences.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PCIe + USB multilink configuration2020-09-18T05:17:22ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:45Zurn:sha1:4acea473f38865e6bc438c1a17ff8f136dc6a0c8
Add PCIe + USB Unique SSC multilink configuration sequences.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add single link USB register sequences2020-09-18T05:17:21ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:44Zurn:sha1:9855d84b6bb1969e45c90d8ed82235a868b99cb6
Add support for single link USB configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add single link SGMII/QSGMII register sequences2020-09-18T05:17:21ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:43Zurn:sha1:9f33b76a35999a20dcea634639b88cf9d486ec9e
Add support for single link SGMII/QSGMII configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals2020-09-18T05:17:21ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:42Zurn:sha1:d66a63666919e9bf27ed9b45c50d35b59c86108d
Include PHY_PLL_CFG as a first register value to configure in
link_cmn_vals array values.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PHY link configuration sequences for single link2020-09-18T05:17:20ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:41Zurn:sha1:cd9aa94737477c9d7cd8595ebc3558b00403f093
Add support to configure link_cmn_vals and xcvr_diag_vals in case of single
link PHY configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add clk changes for multilink configuration2020-09-18T05:17:20ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:40Zurn:sha1:07084c9566635fa1029502e79315a7fe785b80f4
Prepare and enable clock in probe instead of phy_init.
Also, remove phy_exit callback.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-8-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Update PHY reset for multilink configuration2020-09-18T05:17:20ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:39Zurn:sha1:f0f1fa04581f0671837dc60d96cda58127f384c0
For multilink configuration, deassert PHY and link reset after PHY
registers are configured in probe and only check link status in
power_on callback.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-7-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add support for PHY multilink configuration2020-09-18T05:17:19ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:38Zurn:sha1:6bcf3cb300376b73abcb2d241ffce4e909741ac5
Added support for multilink configuration of Torrent PHY. Currently,
maximum two links are supported. In case of multilink configuration,
PHY needs to be configured for both the protocols simultaneously at
the beginning as per the requirement of Torrent PHY.
Also, register sequences for PCIe + SGMII/QSGMII Unique SSC PHY multilink
configurations are added.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-6-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PHY APB reset support2020-09-18T05:17:19ZSwapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:36Zurn:sha1:15c6a048e5f00af108fb9f9e56ca5bd38e11b1a6
Add support for PHY APB reset and make it optional.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-4-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>