wireguard-linux/drivers/phy/qualcomm/Kconfig, branch stable

phy: qcom: qmp-pcie: Add QMP PCIe Multi-PHY driver

2026-08-11T16:54:03Z

Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing single-instance QMP PCIe PHY driver has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Add a dedicated driver for this class of PHY. Match data carries a per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link mode from the TCSR register pointed to by "qcom,link-mode", looks up the corresponding cfg array, and instantiates one qmp_pcie per sub-PHY required by that link mode, registering the clock and #phy-cells = <1> phy providers so consumers can address individual sub-PHYs by index. The driver inherits the phy setting and link-mode programmed by firmware, so only the no_csr reset is used and no phy setting tables are provided. Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or operate as a single x8 link. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Link: https://patch.msgid.link/20260807-glymur_linkmode_0807-v9-2-dd1c7e236e29@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: Add M31 based eUSB2 PHY driver

2025-06-15T16:28:52Z

SM8750 utilizes an eUSB2 PHY from M31. Add the initialization sequences to bring it out of reset and into an operational state. This differs to the M31 USB driver, in that the M31 eUSB2 driver will require a connection to an eUSB2 repeater. This PHY driver will handle the initialization of the associated eUSB2 repeater when required. Reviewed-by: Dmitry Baryshkov Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-6-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: Update description for QCOM based eUSB2 repeater

2025-06-15T16:28:52Z

The eUSB2 repeater that exists in the QCOM PMICs are utilized for several different eUSB2 PHY vendors, such as M31 or Synopsys. Hence, the wording needs to be updated to remove associations to a specific vendor. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Wesley Cheng Signed-off-by: Melody Olvera Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-5-d58de3b41d34@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory

2025-05-14T10:43:37Z

As not only Qualcomm, but also Samsung is using the Synopsys eUSB2 IP (albeit with a different register layout) in their newer SoCs, move the driver out of its vendor sub-directory and rename it to phy-snps-eusb2. Suggested-by: Krzysztof Kozlowski Signed-off-by: Ivaylo Ivanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250504144527.1723980-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul

phy: qcom: uniphy-28lp: add COMMON_CLK dependency

2025-03-16T16:38:10Z

In configurations without CONFIG_COMMON_CLK, the driver fails to build: aarch64-linux-ld: drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.o: in function `qcom_uniphy_pcie_probe': phy-qcom-uniphy-pcie-28lp.c:(.text+0x200): undefined reference to `__clk_hw_register_fixed_rate' aarch64-linux-ld: phy-qcom-uniphy-pcie-28lp.c:(.text+0x238): undefined reference to `of_clk_hw_simple_get' phy-qcom-uniphy-pcie-28lp.c:(.text+0x238): dangerous relocation: unsupported relocation aarch64-linux-ld: phy-qcom-uniphy-pcie-28lp.c:(.text+0x240): undefined reference to `of_clk_hw_simple_get' aarch64-linux-ld: phy-qcom-uniphy-pcie-28lp.c:(.text+0x248): undefined reference to `devm_of_clk_add_hw_provider' Add that as a Kconfig dependencies. Fixes: 74badb8b0b14 ("phy: qcom: Introduce PCIe UNIPHY 28LP driver") Signed-off-by: Arnd Bergmann Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250314154915.4074980-1-arnd@kernel.org Signed-off-by: Vinod Koul

phy: qcom: Introduce PCIe UNIPHY 28LP driver

2025-03-11T11:21:01Z

Add Qualcomm PCIe UNIPHY 28LP driver support present in Qualcomm IPQ5332 SoC and the phy init sequence. Reviewed-by: Dmitry Baryshkov Signed-off-by: Nitheesh Sekar Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20250220094251.230936-3-quic_varada@quicinc.com Signed-off-by: Vinod Koul

phy: qcom: qmp-combo: switch to DRM_AUX_BRIDGE

2023-12-04T14:07:29Z

Switch to using the new DRM_AUX_BRIDGE helper to create the transparent DRM bridge device instead of handcoding corresponding functionality. Acked-by: Vinod Koul Signed-off-by: Dmitry Baryshkov Link: https://patchwork.freedesktop.org/patch/msgid/20231203114333.1305826-3-dmitry.baryshkov@linaro.org

phy: qcom: Introduce M31 USB PHY driver

2023-08-22T13:58:11Z

Add the M31 USB2 phy driver for the USB M31 PHY (https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332 SoCs. Signed-off-by: Varadarajan Narayanan Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul

phy: qcom-qmp-usb: split off the legacy USB+dp_com support

2023-07-12T16:57:41Z

When adding support for some of the platforms (sc7180, sc8180x, sdm845, sm8[1234]50), we added USB PHYs for the combo USB+DP QMP PHYs. Now all such usecases were migrated to use USB+DP Combo driver. To simplify the qcom-qmp-usb PHY driver split the legacy USB+dp_com support into a separate driver. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230531023415.1209301-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul

phy: qcom: add the SGMII SerDes PHY driver

2023-06-21T12:15:10Z

Implement support for the SGMII/SerDes PHY present on various Qualcomm platforms. Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20230619091336.194914-4-brgl@bgdev.pl Signed-off-by: Vinod Koul