wireguard-linux/drivers/pinctrl/aspeed, branch jd/orphan-parallel

pinctrl: aspeed-g6: Add bias controls for 1.8V GPIO banks

2020-09-29T12:38:44Z

These were skipped in the original patches adding pinconf support for the AST2600. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Cc: Johnny Huang Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Use the right pinconf mask

2020-09-29T12:38:44Z

The Aspeed pinconf data structures are split into 'conf' and 'map' types, where the 'conf' struct defines which register and bitfield to manipulate, while the 'map' struct defines what value to write to the register and bitfield. Both structs have a mask member, and the wrong mask was being used to tell the regmap which bits to update. A todo is to look at whether we can remove the mask from the 'map' struct. Fixes: 5f52c853847f ("pinctrl: aspeed: Use masks to describe pinconf bitfields") Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Cc: Johnny Huang Link: https://lore.kernel.org/r/20200910025631.2996342-3-andrew@aj.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Format pinconf debug consistent with pinmux

2020-09-29T12:38:44Z

When displaying which pinconf register and field is being touched, format the field mask so that it's consistent with the way the pinmux portion formats the mask. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200910025631.2996342-2-andrew@aj.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Describe the heartbeat function on ball Y23

2020-07-16T08:32:05Z

The default pinmux configuration for Y23 is to route a heartbeat to drive a LED. Previous revisions of the AST2600 datasheet did not include a description of this function. Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20200701030756.2834657-1-joel@jms.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Improve debug output

2020-07-16T08:31:09Z

We need to iterate over each pin in a group for a function and disable higher priority mux configurations on the pin before finally muxing the relevant function's signal. With the current debug output it is hard to track what register output is relevant to which operation, so break up the actions in the debug output by providing some more context. Before: [ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341 [ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 After: [ 5.298053] Muxing pin 37 for GPIO [ 5.298294] Disabling signal NRI4 for NRI4 [ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.298983] Disabling signal RGMII4RXD1 for RGMII4 [ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.299694] Disabling signal RMII4RXD1 for RMII4 [ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.300396] Enabling signal GPIOE5 for GPIOE5 [ 5.300687] Muxed pin 37 as GPIOE5 Signed-off-by: Andrew Jeffery Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20200701030039.2834418-1-joel@jms.id.au Signed-off-by: Linus Walleij

Merge tag 'v5.5-rc3' into devel

2019-12-28T23:30:37Z

Linux 5.5-rc3

pinctrl: aspeed-g6: Add AST2600 pinconf support

2019-12-13T08:41:01Z

The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-8-andrew@aj.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Use masks to describe pinconf bitfields

2019-12-13T08:40:37Z

Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. Signed-off-by: Johnny Huang [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-7-andrew@aj.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Move aspeed_pin_config_map to separate source file

2019-12-13T08:40:07Z

The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-6-andrew@aj.id.au Signed-off-by: Linus Walleij

pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper

2019-12-13T08:39:47Z

This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery Link: https://lore.kernel.org/r/20191202061432.3996-5-andrew@aj.id.au Signed-off-by: Linus Walleij